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Showing items 21-30 of 176  (18 Page(s) Totally)
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Institution Date Title Author
臺大學術典藏 2018-09-10T15:00:17Z Leakage Power Consumption Reduction Strategy (PCRS) Using Mixed-Vth (MVT) Cells for Low-Voltage/Low-Power SOC G. Lin;C. B. Hsu;J. B. Kuo; G. Lin; C. B. Hsu; J. B. Kuo; JAMES-B KUO
臺大學術典藏 2018-09-10T15:00:17Z Leakage Power Consumption Reduction Strategy (PCRS) Using Mixed-Vth (MVT) Cells for Low-Voltage/Low-Power SOC G. Lin;C. B. Hsu;J. B. Kuo; G. Lin; C. B. Hsu; J. B. Kuo; JAMES-B KUO
臺大學術典藏 2018-09-10T15:00:17Z Critical-path aware power consumption optimization methodology (CAPCOM) using mixed-VTH cells for low-power SOC designs JAMES-B KUO; J. B. Kuo; G. Lin; G. Lin;J. B. Kuo
臺大學術典藏 2018-09-10T15:00:17Z Critical-path aware power consumption optimization methodology (CAPCOM) using mixed-VTH cells for low-power SOC designs JAMES-B KUO; J. B. Kuo; G. Lin; G. Lin;J. B. Kuo
臺大學術典藏 2018-09-10T15:00:17Z Power consumption optimization methodology (PCOM) for low-power/ low-voltage 32-bit microprocessor circuit design via MTCMOS C. B. Hsu;J. B. Kuo; C. B. Hsu; J. B. Kuo; JAMES-B KUO
臺大學術典藏 2018-09-10T15:00:17Z Power consumption optimization methodology (PCOM) for low-power/ low-voltage 32-bit microprocessor circuit design via MTCMOS C. B. Hsu;J. B. Kuo; C. B. Hsu; J. B. Kuo; JAMES-B KUO
臺大學術典藏 2018-09-10T15:00:17Z Back-Gate-Baias Induced Floating-Body-Related Subthreshold Characteristics of SOI NMOS Device S. K. Hu;D. H. Lung;J. B. Kuo;D. Chen; S. K. Hu; D. H. Lung; J. B. Kuo; D. Chen; JAMES-B KUO
臺大學術典藏 2018-09-10T15:00:17Z Back-Gate-Baias Induced Floating-Body-Related Subthreshold Characteristics of SOI NMOS Device S. K. Hu;D. H. Lung;J. B. Kuo;D. Chen; S. K. Hu; D. H. Lung; J. B. Kuo; D. Chen; JAMES-B KUO
臺大學術典藏 2018-09-10T09:50:25Z Function of the Upper/Lower Parasitic BJTs in 40nm PD SOI NMOS Device due to the Back-Gate Bias Effect A. P. Chuang;S. I. Su;Z. H. Yang;J. B. Kuo;D. Chen;C. S. Yeh; A. P. Chuang; S. I. Su; Z. H. Yang; J. B. Kuo; D. Chen; C. S. Yeh; JAMES-B KUO
臺大學術典藏 2018-09-10T09:50:25Z Function of the Upper/Lower Parasitic BJTs in 40nm PD SOI NMOS Device due to the Back-Gate Bias Effect A. P. Chuang;S. I. Su;Z. H. Yang;J. B. Kuo;D. Chen;C. S. Yeh; A. P. Chuang; S. I. Su; Z. H. Yang; J. B. Kuo; D. Chen; C. S. Yeh; JAMES-B KUO

Showing items 21-30 of 176  (18 Page(s) Totally)
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