臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)

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臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)

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	2019臺灣學術機構典藏研討會
	機構典藏系統RC7版本已發佈

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Showing items 76-85 of 176 (18 Page(s) Totally)
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Institution	Date	Title	Author
臺大學術典藏	2018-09-10T07:41:38Z	Floating-Body-Effect-Related Gate Tunneling Leakage Current Phenomenon of 40nm PD SOI NMOS Device	H. J. Hung;J. B. Kuo;C. T. Tsai;D. Chen; H. J. Hung; J. B. Kuo; C. T. Tsai; D. Chen; JAMES-B KUO
臺大學術典藏	2018-09-10T07:41:38Z	Floating-Body-Effect-Related Gate Tunneling Leakage Current Phenomenon of 40nm PD SOI NMOS Device	H. J. Hung;J. B. Kuo;C. T. Tsai;D. Chen; H. J. Hung; J. B. Kuo; C. T. Tsai; D. Chen; JAMES-B KUO
臺大學術典藏	2018-09-10T07:41:38Z	Low-Voltage CMOS VLSI Circuits	J. B. Kuo; J. H. Lou; JAMES-B KUO
臺大學術典藏	2018-09-10T07:41:37Z	Shallow Trench Isolated-Related Narrow Channel Effect on Kink Effect and Breakdown Behavior of 40nm PD SOI NMOS Device	J. I. Lu;H. J. Hung;J. B. Kuo;D. Chen;C. S. Yeh;C. T. Tsai; J. I. Lu; H. J. Hung; J. B. Kuo; D. Chen; C. S. Yeh; C. T. Tsai; JAMES-B KUO
臺大學術典藏	2018-09-10T07:41:37Z	Shallow Trench Isolated-Related Narrow Channel Effect on Kink Effect and Breakdown Behavior of 40nm PD SOI NMOS Device	J. I. Lu;H. J. Hung;J. B. Kuo;D. Chen;C. S. Yeh;C. T. Tsai; J. I. Lu; H. J. Hung; J. B. Kuo; D. Chen; C. S. Yeh; C. T. Tsai; JAMES-B KUO
臺大學術典藏	2018-09-10T07:41:37Z	Floating-body-effect-related gate tunneling leakage current phenomenon of 40nm PD SOI NMOS device	H. J. Hung;J. I. Lu;J. B. Kuo;D. Chen;C. S. Yeh; H. J. Hung; J. I. Lu; J. B. Kuo; D. Chen; C. S. Yeh; JAMES-B KUO
臺大學術典藏	2018-09-10T07:41:37Z	Floating-body-effect-related gate tunneling leakage current phenomenon of 40nm PD SOI NMOS device	H. J. Hung;J. I. Lu;J. B. Kuo;D. Chen;C. S. Yeh; H. J. Hung; J. I. Lu; J. B. Kuo; D. Chen; C. S. Yeh; JAMES-B KUO
臺大學術典藏	2018-09-10T07:41:37Z	0.5V SOI CMOS Dual-Threshold Circuit Technique Via DTMOS for Design Optimization of Low-Power VLSI System Applications	W. J. H. Lin;C. Y. Chien;J. B. Kuo; W. J. H. Lin; C. Y. Chien; J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T07:41:37Z	0.5V SOI CMOS Dual-Threshold Circuit Technique Via DTMOS for Design Optimization of Low-Power VLSI System Applications	W. J. H. Lin;C. Y. Chien;J. B. Kuo; W. J. H. Lin; C. Y. Chien; J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T07:41:37Z	Design Optimization of Low-Power 90nm CMOS SOC Applications Using 0.5V Bulk PMOS Dynamic-Threshold with Dual Threshold (MTCMOS) BP-DTMOS-DT Technique	C. H. Lin;J. B. Kuo; C. H. Lin; J. B. Kuo; JAMES-B KUO

Showing items 76-85 of 176 (18 Page(s) Totally)
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