臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)

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臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)

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机构	日期	题名	作者
臺大學術典藏	2018-09-10T08:47:24Z	Test-Clock Domain Optimization for Peak Power-Supply Noise Reduction During Scan	R.Y. Wen; Y.C. Huang; M.H. Tsai; K.Y. Liao; J. C.-M. Li; M.-T. Chang; M.-H. Tsai; C.-M. Tseng; H.-C. Li; CHIEN-MO LI
臺大學術典藏	2018-09-10T08:47:24Z	An At-speed Self-testable Technique for the High Speed Domino Adder	C. Liu; C. Liu; J. C.-M. Li; C.-P. Chen; CHIEN-MO LI; Y. Wang; M. Hsieh
臺大學術典藏	2018-09-10T08:19:10Z	Method for adjusting clock domain during layout of integrated circuit and associated computer readable medium	J. Y. Wen;J. C. M. Li; J. Y. Wen; J. C. M. Li; CHIEN-MO LI
臺大學術典藏	2018-09-10T08:19:10Z	Method for adjusting clock domain during layout of integrated circuit and associated computer readable medium	J. Y. Wen;J. C. M. Li; J. Y. Wen; J. C. M. Li; CHIEN-MO LI
臺大學術典藏	2018-09-10T08:19:09Z	DFT and Minimum Leakage Pattern Generation for Static Power Reduction During Test and Burn-in	W.-C. Kao;W.-S. Chuang;H.-T. Lin;J. C.-M. Li;V, Manquinho; W.-C. Kao; W.-S. Chuang; H.-T. Lin; J. C.-M. Li; V, Manquinho; CHIEN-MO LI
臺大學術典藏	2018-09-10T08:19:09Z	DFT and Minimum Leakage Pattern Generation for Static Power Reduction During Test and Burn-in	W.-C. Kao;W.-S. Chuang;H.-T. Lin;J. C.-M. Li;V, Manquinho; W.-C. Kao; W.-S. Chuang; H.-T. Lin; J. C.-M. Li; V, Manquinho; CHIEN-MO LI
臺大學術典藏	2018-09-10T07:43:08Z	Fault Modeling and Testing of Retention Flip-Flops in Low Power Designs	B. C. Bai;A. K Li;J. C.M. Li;K. C. Wu; B. C. Bai; A. K Li; J. C.M. Li; K. C. Wu; CHIEN-MO LI
臺大學術典藏	2018-09-10T07:43:08Z	Fault Modeling and Testing of Retention Flip-Flops in Low Power Designs	B. C. Bai;A. K Li;J. C.M. Li;K. C. Wu; B. C. Bai; A. K Li; J. C.M. Li; K. C. Wu; CHIEN-MO LI
臺大學術典藏	2018-09-10T07:43:08Z	BIST Design Optimization for Large-Scale Embedded Memory Cores	T.-F. Chien;W.-C. Chao;J. C.-M. Li;K.-Y. Liao;Y.-W. Chang;M.-T. Chang;M.-H. Tsai;C.-M. Tseng; T.-F. Chien; W.-C. Chao; J. C.-M. Li; K.-Y. Liao; Y.-W. Chang; M.-T. Chang; M.-H. Tsai; C.-M. Tseng; CHIEN-MO LI
臺大學術典藏	2018-09-10T07:43:08Z	BIST Design Optimization for Large-Scale Embedded Memory Cores	T.-F. Chien;W.-C. Chao;J. C.-M. Li;K.-Y. Liao;Y.-W. Chang;M.-T. Chang;M.-H. Tsai;C.-M. Tseng; T.-F. Chien; W.-C. Chao; J. C.-M. Li; K.-Y. Liao; Y.-W. Chang; M.-T. Chang; M.-H. Tsai; C.-M. Tseng; CHIEN-MO LI

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