| 臺大學術典藏 |
2018-09-10T09:25:31Z |
Thermal-aware Test Schedule and TAM Co-Optimization for Three Dimensional IC
|
C. J. Shih;C. Y. Hsu;C. Y. Kou;J. C. M. Li;J. C. Rau;K. Chakrabarty; C. J. Shih; C. Y. Hsu; C. Y. Kou; J. C. M. Li; J. C. Rau; K. Chakrabarty; CHIEN-MO LI |
| 臺大學術典藏 |
2018-09-10T09:25:31Z |
Launch-on-Shift Test Generation for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains,
|
S. Wu;L. T. Wang;X. Wen;W. B. Jone;M. S. Hsiao;F. Li;J. C. M. Li;J. L. Huang; S. Wu; L. T. Wang; X. Wen; W. B. Jone; M. S. Hsiao; F. Li; J. C. M. Li; J. L. Huang; CHIEN-MO LI; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T09:25:31Z |
Launch-on-Shift Test Generation for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains,
|
S. Wu;L. T. Wang;X. Wen;W. B. Jone;M. S. Hsiao;F. Li;J. C. M. Li;J. L. Huang; S. Wu; L. T. Wang; X. Wen; W. B. Jone; M. S. Hsiao; F. Li; J. C. M. Li; J. L. Huang; CHIEN-MO LI; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T09:25:31Z |
An At-speed Test Technique for High-speed High-order Adder by a 6.4-GHz 64-bit Domino Adder Example
|
Y. S. Wang;M. H. Hsieh;J. C. M. Li;C. C. P. Chen; Y. S. Wang; M. H. Hsieh; J. C. M. Li; C. C. P. Chen; CHIEN-MO LI |
| 臺大學術典藏 |
2018-09-10T09:25:31Z |
An At-speed Test Technique for High-speed High-order Adder by a 6.4-GHz 64-bit Domino Adder Example
|
Y. S. Wang;M. H. Hsieh;J. C. M. Li;C. C. P. Chen; Y. S. Wang; M. H. Hsieh; J. C. M. Li; C. C. P. Chen; CHIEN-MO LI |
| 臺大學術典藏 |
2018-09-10T09:25:31Z |
Transient IR-drop Analysis for At-speed Testing Using Representative Random Walk,
|
M. H. Tsai;W. S. Ting;J. C. M. Li; M. H. Tsai; W. S. Ting; J. C. M. Li; CHIEN-MO LI |
| 臺大學術典藏 |
2018-09-10T09:25:31Z |
Transient IR-drop Analysis for At-speed Testing Using Representative Random Walk,
|
M. H. Tsai;W. S. Ting;J. C. M. Li; M. H. Tsai; W. S. Ting; J. C. M. Li; CHIEN-MO LI |
| 臺大學術典藏 |
2018-09-10T09:25:31Z |
GPU-Based Massively Parallel N-Detect Transition Delay Fault ATPG,
|
K. Y. Liao; S. C. Hsu; J. C. M. Li; CHIEN-MO LI |
| 臺大學術典藏 |
2018-09-10T09:25:31Z |
Multi-Mode Automatic Test Pattern Generation for Dynamic Voltage and Frequency Scaling Designs
|
B. C. Bai;J. C. M. Li; B. C. Bai; J. C. M. Li; CHIEN-MO LI |
| 臺大學術典藏 |
2018-09-10T09:25:31Z |
Multi-Mode Automatic Test Pattern Generation for Dynamic Voltage and Frequency Scaling Designs
|
B. C. Bai;J. C. M. Li; B. C. Bai; J. C. M. Li; CHIEN-MO LI |
| 臺大學術典藏 |
2018-09-10T09:25:31Z |
Testing of TSV-induced Small Delay Faults for Three Dimensional Integrated Circuits,
|
C.Y. Kuo;C. J. Shih;J. C. M. Li;K. Chakrabarty; C.Y. Kuo; C. J. Shih; J. C. M. Li; K. Chakrabarty; CHIEN-MO LI |
| 臺大學術典藏 |
2018-09-10T09:25:31Z |
Testing of TSV-induced Small Delay Faults for Three Dimensional Integrated Circuits,
|
C.Y. Kuo;C. J. Shih;J. C. M. Li;K. Chakrabarty; C.Y. Kuo; C. J. Shih; J. C. M. Li; K. Chakrabarty; CHIEN-MO LI |
| 臺大學術典藏 |
2018-09-10T09:25:30Z |
A Secure Test Wrapper Design against Internal and Boundary Scan Attacks for Embedded Cores
|
G.M. Chiu;J. C. M. Li; G.M. Chiu; J. C. M. Li; CHIEN-MO LI |
| 臺大學術典藏 |
2018-09-10T09:25:30Z |
A Secure Test Wrapper Design against Internal and Boundary Scan Attacks for Embedded Cores
|
G.M. Chiu;J. C. M. Li; G.M. Chiu; J. C. M. Li; CHIEN-MO LI |
| 臺大學術典藏 |
2018-09-10T08:47:24Z |
An Asynchronous Design for Testability and Implementation in Thin-film Transistor Technology
|
C. H. Cheng; J. C. M. Li; CHIEN-MO LI |
| 臺大學術典藏 |
2018-09-10T08:47:24Z |
Test-Clock Domain Optimization for Peak Power-Supply Noise Reduction During Scan
|
R.Y. Wen; Y.C. Huang; M.H. Tsai; K.Y. Liao; J. C.-M. Li; M.-T. Chang; M.-H. Tsai; C.-M. Tseng; H.-C. Li; CHIEN-MO LI |
| 臺大學術典藏 |
2018-09-10T08:47:24Z |
An At-speed Self-testable Technique for the High Speed Domino Adder
|
C. Liu; C. Liu; J. C.-M. Li; C.-P. Chen; CHIEN-MO LI; Y. Wang; M. Hsieh |
| 臺大學術典藏 |
2018-09-10T08:19:10Z |
Method for adjusting clock domain during layout of integrated circuit and associated computer readable medium
|
J. Y. Wen;J. C. M. Li; J. Y. Wen; J. C. M. Li; CHIEN-MO LI |
| 臺大學術典藏 |
2018-09-10T08:19:10Z |
Method for adjusting clock domain during layout of integrated circuit and associated computer readable medium
|
J. Y. Wen;J. C. M. Li; J. Y. Wen; J. C. M. Li; CHIEN-MO LI |
| 臺大學術典藏 |
2018-09-10T08:19:09Z |
DFT and Minimum Leakage Pattern Generation for Static Power Reduction During Test and Burn-in
|
W.-C. Kao;W.-S. Chuang;H.-T. Lin;J. C.-M. Li;V, Manquinho; W.-C. Kao; W.-S. Chuang; H.-T. Lin; J. C.-M. Li; V, Manquinho; CHIEN-MO LI |
| 臺大學術典藏 |
2018-09-10T08:19:09Z |
DFT and Minimum Leakage Pattern Generation for Static Power Reduction During Test and Burn-in
|
W.-C. Kao;W.-S. Chuang;H.-T. Lin;J. C.-M. Li;V, Manquinho; W.-C. Kao; W.-S. Chuang; H.-T. Lin; J. C.-M. Li; V, Manquinho; CHIEN-MO LI |
| 臺大學術典藏 |
2018-09-10T07:43:08Z |
Fault Modeling and Testing of Retention Flip-Flops in Low Power Designs
|
B. C. Bai;A. K Li;J. C.M. Li;K. C. Wu; B. C. Bai; A. K Li; J. C.M. Li; K. C. Wu; CHIEN-MO LI |
| 臺大學術典藏 |
2018-09-10T07:43:08Z |
Fault Modeling and Testing of Retention Flip-Flops in Low Power Designs
|
B. C. Bai;A. K Li;J. C.M. Li;K. C. Wu; B. C. Bai; A. K Li; J. C.M. Li; K. C. Wu; CHIEN-MO LI |
| 臺大學術典藏 |
2018-09-10T07:43:08Z |
BIST Design Optimization for Large-Scale Embedded Memory Cores
|
T.-F. Chien;W.-C. Chao;J. C.-M. Li;K.-Y. Liao;Y.-W. Chang;M.-T. Chang;M.-H. Tsai;C.-M. Tseng; T.-F. Chien; W.-C. Chao; J. C.-M. Li; K.-Y. Liao; Y.-W. Chang; M.-T. Chang; M.-H. Tsai; C.-M. Tseng; CHIEN-MO LI |
| 臺大學術典藏 |
2018-09-10T07:43:08Z |
BIST Design Optimization for Large-Scale Embedded Memory Cores
|
T.-F. Chien;W.-C. Chao;J. C.-M. Li;K.-Y. Liao;Y.-W. Chang;M.-T. Chang;M.-H. Tsai;C.-M. Tseng; T.-F. Chien; W.-C. Chao; J. C.-M. Li; K.-Y. Liao; Y.-W. Chang; M.-T. Chang; M.-H. Tsai; C.-M. Tseng; CHIEN-MO LI |
