臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)

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Showing items 31-40 of 76 (8 Page(s) Totally)
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Institution	Date	Title	Author
臺大學術典藏	2018-09-10T09:25:31Z	Transient IR-drop Analysis for At-speed Testing Using Representative Random Walk,	M. H. Tsai;W. S. Ting;J. C. M. Li; M. H. Tsai; W. S. Ting; J. C. M. Li; CHIEN-MO LI
臺大學術典藏	2018-09-10T09:25:31Z	Transient IR-drop Analysis for At-speed Testing Using Representative Random Walk,	M. H. Tsai;W. S. Ting;J. C. M. Li; M. H. Tsai; W. S. Ting; J. C. M. Li; CHIEN-MO LI
臺大學術典藏	2018-09-10T09:25:31Z	GPU-Based Massively Parallel N-Detect Transition Delay Fault ATPG,	K. Y. Liao; S. C. Hsu; J. C. M. Li; CHIEN-MO LI
臺大學術典藏	2018-09-10T09:25:31Z	Multi-Mode Automatic Test Pattern Generation for Dynamic Voltage and Frequency Scaling Designs	B. C. Bai;J. C. M. Li; B. C. Bai; J. C. M. Li; CHIEN-MO LI
臺大學術典藏	2018-09-10T09:25:31Z	Multi-Mode Automatic Test Pattern Generation for Dynamic Voltage and Frequency Scaling Designs	B. C. Bai;J. C. M. Li; B. C. Bai; J. C. M. Li; CHIEN-MO LI
臺大學術典藏	2018-09-10T09:25:31Z	Testing of TSV-induced Small Delay Faults for Three Dimensional Integrated Circuits,	C.Y. Kuo;C. J. Shih;J. C. M. Li;K. Chakrabarty; C.Y. Kuo; C. J. Shih; J. C. M. Li; K. Chakrabarty; CHIEN-MO LI
臺大學術典藏	2018-09-10T09:25:31Z	Testing of TSV-induced Small Delay Faults for Three Dimensional Integrated Circuits,	C.Y. Kuo;C. J. Shih;J. C. M. Li;K. Chakrabarty; C.Y. Kuo; C. J. Shih; J. C. M. Li; K. Chakrabarty; CHIEN-MO LI
臺大學術典藏	2018-09-10T09:25:30Z	A Secure Test Wrapper Design against Internal and Boundary Scan Attacks for Embedded Cores	G.M. Chiu;J. C. M. Li; G.M. Chiu; J. C. M. Li; CHIEN-MO LI
臺大學術典藏	2018-09-10T09:25:30Z	A Secure Test Wrapper Design against Internal and Boundary Scan Attacks for Embedded Cores	G.M. Chiu;J. C. M. Li; G.M. Chiu; J. C. M. Li; CHIEN-MO LI
臺大學術典藏	2018-09-10T08:47:24Z	An Asynchronous Design for Testability and Implementation in Thin-film Transistor Technology	C. H. Cheng; J. C. M. Li; CHIEN-MO LI

Showing items 31-40 of 76 (8 Page(s) Totally)
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