| 臺大學術典藏 |
2018-09-10T08:47:24Z |
Test-Clock Domain Optimization for Peak Power-Supply Noise Reduction During Scan
|
R.Y. Wen; Y.C. Huang; M.H. Tsai; K.Y. Liao; J. C.-M. Li; M.-T. Chang; M.-H. Tsai; C.-M. Tseng; H.-C. Li; CHIEN-MO LI |
| 臺大學術典藏 |
2018-09-10T08:47:24Z |
An At-speed Self-testable Technique for the High Speed Domino Adder
|
C. Liu; C. Liu; J. C.-M. Li; C.-P. Chen; CHIEN-MO LI; Y. Wang; M. Hsieh |
| 臺大學術典藏 |
2018-09-10T08:19:10Z |
Method for adjusting clock domain during layout of integrated circuit and associated computer readable medium
|
J. Y. Wen;J. C. M. Li; J. Y. Wen; J. C. M. Li; CHIEN-MO LI |
| 臺大學術典藏 |
2018-09-10T08:19:10Z |
Method for adjusting clock domain during layout of integrated circuit and associated computer readable medium
|
J. Y. Wen;J. C. M. Li; J. Y. Wen; J. C. M. Li; CHIEN-MO LI |
| 臺大學術典藏 |
2018-09-10T08:19:09Z |
DFT and Minimum Leakage Pattern Generation for Static Power Reduction During Test and Burn-in
|
W.-C. Kao;W.-S. Chuang;H.-T. Lin;J. C.-M. Li;V, Manquinho; W.-C. Kao; W.-S. Chuang; H.-T. Lin; J. C.-M. Li; V, Manquinho; CHIEN-MO LI |
| 臺大學術典藏 |
2018-09-10T08:19:09Z |
DFT and Minimum Leakage Pattern Generation for Static Power Reduction During Test and Burn-in
|
W.-C. Kao;W.-S. Chuang;H.-T. Lin;J. C.-M. Li;V, Manquinho; W.-C. Kao; W.-S. Chuang; H.-T. Lin; J. C.-M. Li; V, Manquinho; CHIEN-MO LI |
| 臺大學術典藏 |
2018-09-10T07:43:08Z |
Fault Modeling and Testing of Retention Flip-Flops in Low Power Designs
|
B. C. Bai;A. K Li;J. C.M. Li;K. C. Wu; B. C. Bai; A. K Li; J. C.M. Li; K. C. Wu; CHIEN-MO LI |
| 臺大學術典藏 |
2018-09-10T07:43:08Z |
Fault Modeling and Testing of Retention Flip-Flops in Low Power Designs
|
B. C. Bai;A. K Li;J. C.M. Li;K. C. Wu; B. C. Bai; A. K Li; J. C.M. Li; K. C. Wu; CHIEN-MO LI |
| 臺大學術典藏 |
2018-09-10T07:43:08Z |
BIST Design Optimization for Large-Scale Embedded Memory Cores
|
T.-F. Chien;W.-C. Chao;J. C.-M. Li;K.-Y. Liao;Y.-W. Chang;M.-T. Chang;M.-H. Tsai;C.-M. Tseng; T.-F. Chien; W.-C. Chao; J. C.-M. Li; K.-Y. Liao; Y.-W. Chang; M.-T. Chang; M.-H. Tsai; C.-M. Tseng; CHIEN-MO LI |
| 臺大學術典藏 |
2018-09-10T07:43:08Z |
BIST Design Optimization for Large-Scale Embedded Memory Cores
|
T.-F. Chien;W.-C. Chao;J. C.-M. Li;K.-Y. Liao;Y.-W. Chang;M.-T. Chang;M.-H. Tsai;C.-M. Tseng; T.-F. Chien; W.-C. Chao; J. C.-M. Li; K.-Y. Liao; Y.-W. Chang; M.-T. Chang; M.-H. Tsai; C.-M. Tseng; CHIEN-MO LI |
| 臺大學術典藏 |
2018-09-10T07:43:08Z |
Electronic Design Automation
|
J. C.-M. Li;M. Hsiao; J. C.-M. Li; M. Hsiao; CHIEN-MO LI |
| 臺大學術典藏 |
2018-09-10T07:43:08Z |
Electronic Design Automation
|
J. C.-M. Li;M. Hsiao; J. C.-M. Li; M. Hsiao; CHIEN-MO LI |
| 臺大學術典藏 |
2018-09-10T07:43:07Z |
Very-Low-Voltage Testing of Amorphous Silicon TFT Circuits
|
Shiue-Tsung Shen,;Wei-Hsiao Liu,;En-Hua Ma,;J. C.-M. Li,;I-Chun Cheng,; Shiue-Tsung Shen,; Wei-Hsiao Liu,; En-Hua Ma,; J. C.-M. Li,; I-Chun Cheng,; I-CHUN CHENG; CHIEN-MO LI |
| 臺大學術典藏 |
2018-09-10T07:43:07Z |
Very-Low-Voltage Testing of Amorphous Silicon TFT Circuits
|
Shiue-Tsung Shen,;Wei-Hsiao Liu,;En-Hua Ma,;J. C.-M. Li,;I-Chun Cheng,; Shiue-Tsung Shen,; Wei-Hsiao Liu,; En-Hua Ma,; J. C.-M. Li,; I-Chun Cheng,; I-CHUN CHENG; CHIEN-MO LI |
| 臺大學術典藏 |
2018-09-10T07:43:06Z |
Time-space test response compaction and diagnosis based on BCH codes
|
F. M. Wang;W.-C. Wang;J. C-M. Li; F. M. Wang; W.-C. Wang; J. C-M. Li; CHIEN-MO LI |
| 臺大學術典藏 |
2018-09-10T07:43:06Z |
Time-space test response compaction and diagnosis based on BCH codes
|
F. M. Wang;W.-C. Wang;J. C-M. Li; F. M. Wang; W.-C. Wang; J. C-M. Li; CHIEN-MO LI |
| 臺大學術典藏 |
2018-09-10T07:43:06Z |
Bridging Fault Diagnosis to Identify the Layer of Systematic Defects
|
B. R. Chen;J. C.M. Li; B. R. Chen; J. C.M. Li; CHIEN-MO LI |
| 臺大學術典藏 |
2018-09-10T07:43:06Z |
Bridging Fault Diagnosis to Identify the Layer of Systematic Defects
|
B. R. Chen;J. C.M. Li; B. R. Chen; J. C.M. Li; CHIEN-MO LI |
| 臺大學術典藏 |
2018-09-10T07:09:34Z |
Phase Noise Testing of Single Chip TV Tuners,
|
P.-C. Lin; C.-H. Hsu; J. C.-M. Li; C.-M. Chiang; C.-J. Pan,; CHIEN-MO LI |
| 臺大學術典藏 |
2018-09-10T07:09:34Z |
An Asynchronous DFT Technique for TFT Macroelectronics
|
C. H. Cheng; C.-H. Hsu; J. C.M. Li; CHIEN-MO LI |
| 臺大學術典藏 |
2018-09-10T07:09:34Z |
A Dual-rail Asynchronous Scan Chain Design and Its Implementation in TFT Technology
|
C. H. Cheng; J. C.M. Li; CHIEN-MO LI |
| 臺大學術典藏 |
2018-09-10T07:09:34Z |
Transition Fault Diagnosis Using At-speed Scan Patterns with Multiple Capture Clocks
|
Shang-Feng Chao;J. C.-M. Li; Shang-Feng Chao; J. C.-M. Li; CHIEN-MO LI |
| 臺大學術典藏 |
2018-09-10T07:09:34Z |
Transition Fault Diagnosis Using At-speed Scan Patterns with Multiple Capture Clocks
|
Shang-Feng Chao;J. C.-M. Li; Shang-Feng Chao; J. C.-M. Li; CHIEN-MO LI |
| 臺大學術典藏 |
2018-09-10T07:09:33Z |
Simultaneous capture and shift power reduction test pattern generator for scan testing
|
CHIEN-MO LI; J. C.M. Li; H.T. Lin |
| 臺大學術典藏 |
2018-09-10T07:09:32Z |
Effective and Economic Phase Noise Testing for Single-Chip TV Tuners
|
J. C.-M. Li; P.-C. Lin; P.-C. Chiang; C.-M. Pan; C.W. Tseng; CHIEN-MO LI |
| 臺大學術典藏 |
2018-09-10T07:09:32Z |
Survey of Scan Chain Diagnosis
|
Y. Huang;R Guo;W.T. Cheng;J. C.-M. Li; Y. Huang; R Guo; W.T. Cheng; J. C.-M. Li; CHIEN-MO LI |
| 臺大學術典藏 |
2018-09-10T07:09:32Z |
Survey of Scan Chain Diagnosis
|
Y. Huang;R Guo;W.T. Cheng;J. C.-M. Li; Y. Huang; R Guo; W.T. Cheng; J. C.-M. Li; CHIEN-MO LI |
| 臺大學術典藏 |
2018-09-10T06:37:54Z |
Column Parity Row Selection (CPRS) BIST Diagnosis Technique: Modeling and Analysis
|
J. C.-M. Li; Hung-Mao Lin; Fang Min Wang; CHIEN-MO LI |
| 臺大學術典藏 |
2018-09-10T06:37:54Z |
Cyclic-CPRS : A Diagnosis Technique for BISTed Circuits for Nano-meter Technologies
|
C.Y. Lee; H.M. Lin; F.M. Wang; J. C. M. Li; CHIEN-MO LI |
| 臺大學術典藏 |
2018-09-10T06:03:19Z |
Jump Simulation: A Fast and Precise Scan Chain Diagnosis Technique
|
Y. L Kao; W. S. Chuang; J. C. M Li; CHIEN-MO LI |
| 臺大學術典藏 |
2018-09-10T06:03:18Z |
CRC BIST: A Low Peak Power Self Technique
|
Bo-Hua Chen; J. C.-M. Li; CHIEN-MO LI |
| 臺大學術典藏 |
2018-09-10T05:29:22Z |
Jump Scan: A DFT Technique for Low Power Testing,
|
M.H. Chiu; J. C. M Li; CHIEN-MO LI |
| 臺大學術典藏 |
2018-09-10T05:29:21Z |
Effective and Economic Phase Noise Testing for Single Chip TV Tuners
|
P.C. Lin; J. C.-M. Li; Chih-Ming Chiang; Chuo-Jan Pan; CHIEN-MO LI |
| 臺大學術典藏 |
2018-09-10T04:59:51Z |
ELF-Murphy Data on Defects and Test Sets
|
E. J. McCluskey; A. Alyamani; J. C. M. Li; C. W. Tseng; E. Volkerink; F. F. Feriani; E. Li; S. Mitra; CHIEN-MO LI |
| 臺大學術典藏 |
2011-01 |
Row-linear feedback shift register-column x-masking technique for simultaneous testing of many-core system chips
|
W.C. Wang; J.C.M Li; CHIEN-MO LI |
| 臺大學術典藏 |
2005-10 |
Column Parity and Row Select (CPRS): BIST Diagnosis for Errors in Multiple Scan Chains
|
CHIEN-MO LI; H.M. Lin; J. C. M. Li |
