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"jou jy"
Showing items 31-40 of 67 (7 Page(s) Totally)
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| 國立交通大學 |
2014-12-08T15:27:36Z |
A power modeling and characterization method for the CMOS standard cell library
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Lin, JY; Shen, WZ; Jou, JY |
| 國立交通大學 |
2014-12-08T15:27:29Z |
A power modeling and characterization method for macrocells using structure information
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Lin, JY; Shen, WZ; Jou, JY |
| 國立交通大學 |
2014-12-08T15:27:27Z |
Power driven partial scan
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Jou, JY; Nien, MC |
| 國立交通大學 |
2014-12-08T15:27:20Z |
Compatible class encoding in hyper-function decomposition for FPGA synthesis
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Jiang, JHR; Jou, JY; Huang, JD |
| 國立交通大學 |
2014-12-08T15:27:12Z |
Hierarchical floorplan design on the Internet
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Lin, JH; Jou, JY; Jiang, HR |
| 國立交通大學 |
2014-12-08T15:26:58Z |
A novel approach for functional coverage measurement in HDL
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Liu, CNJ; Chang, CY; Jou, JY; Lai, MC; Juan, HM |
| 國立交通大學 |
2014-12-08T15:26:54Z |
Title on flip-flop inference in HDL synthesis
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Lin, HM; Jou, JY |
| 國立交通大學 |
2014-12-08T15:26:53Z |
On generation of the minimum pattern set for data path elements in SoC design verification based on port order fault model
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Wang, CY; Tung, SW; Jou, JY |
| 國立交通大學 |
2014-12-08T15:26:51Z |
Automatic functional vector generation using the interacting FSM model
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Liu, CNJ; Yen, CC; Jou, JY |
| 國立交通大學 |
2014-12-08T15:26:50Z |
On placement and routing of wafer scale memory
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Sung, LA; Jiang, IHR; Chang, YW; Jou, JY; Wu, JC; Feng, TS |
Showing items 31-40 of 67 (7 Page(s) Totally)
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