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Institution Date Title Author
國立交通大學 2017-04-21T06:49:36Z Stable High-Density FD/SOI SRAM with Selective Back-Gate Bias Using Dual Buried Oxide Kim, Keunwoo; Kuang, Jente B.; Gebara, Fadi; Ngo, Hung C.; Chuang, Ching-Te; Nowka, Kevin J.
國立交通大學 2014-12-08T15:42:37Z An on-chip test structure and digital measurement method for statistical characterization of local random variability in a process Mukhopadhyay, Saibal; Kim, Keunwoo; Jenkins, Keith A.; Chuang, Ching-Te; Roy, Kaushik
國立交通大學 2014-12-08T15:10:57Z Optimal design of triple-gate devices for high-performance and low-power applications Chiang, Meng-Hsueh; Lin, Jeng-Nan; Kim, Keunwoo; Chuang, Ching-Te
國立交通大學 2014-12-08T15:10:02Z Selective Device Structure Scaling and Parasitics Engineering: A Way to Extend the Technology Roadmap Wei, Lan; Deng, Jie; Chang, Li-Wen; Kim, Keunwoo; Chuang, Ching-Te; Wong, H. -S. Philip
國立交通大學 2014-12-08T15:08:11Z TCAD/Physics-Based Analysis of High-Density Dual-BOX FD/SOI SRAM Cell With Improved Stability Kim, Keunwoo; Kuang, Jente B.; Gebara, Fadi H.; Ngo, Hung C.; Chuang, Ching-Te; Nowka, Kevin J.
國立成功大學 2012-05 Assessment of structure variation in silicon nanowire FETs and impact on SRAM Liao, Yi-Bo; Chiang, Meng-Hsueh; Kim, Keunwoo; Hsu, Wei-Chou

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