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Institution Date Title Author
臺大學術典藏 2020-06-11T06:34:57Z A digital bang-bang phase-locked loop with automatic loop gain control and loop latency reduction Kuan, T.-K.;Liu, S.-I.; Kuan, T.-K.; Liu, S.-I.; SHEN-IUAN LIU
臺大學術典藏 2020-06-11T06:34:57Z A digital bang-bang phase-locked loop with automatic loop gain control and loop latency reduction Kuan, T.-K.;Liu, S.-I.; Kuan, T.-K.; Liu, S.-I.; SHEN-IUAN LIU
臺大學術典藏 2020-06-11T06:34:55Z A Subharmonically Injection-Locked All-Digital PLL Without Main Divider Zeng, K.-H.;Kuan, T.-K.;Liu, S.-I.; Zeng, K.-H.; Kuan, T.-K.; Liu, S.-I.; SHEN-IUAN LIU
臺大學術典藏 2020-06-11T06:34:55Z A Subharmonically Injection-Locked All-Digital PLL Without Main Divider Zeng, K.-H.;Kuan, T.-K.;Liu, S.-I.; Zeng, K.-H.; Kuan, T.-K.; Liu, S.-I.; SHEN-IUAN LIU
臺大學術典藏 2020-06-11T06:34:51Z A Bang-Bang Phase-Locked Loop Using Automatic Loop Gain Control and Loop Latency Reduction Techniques Kuan, T.-K.;Liu, S.-I.; Kuan, T.-K.; Liu, S.-I.; SHEN-IUAN LIU
臺大學術典藏 2020-06-11T06:34:51Z A Bang-Bang Phase-Locked Loop Using Automatic Loop Gain Control and Loop Latency Reduction Techniques Kuan, T.-K.;Liu, S.-I.; Kuan, T.-K.; Liu, S.-I.; SHEN-IUAN LIU
臺大學術典藏 2020-06-11T06:34:48Z A digital MDLL using switched biasing technique to reduce low-frequency phase noise Chiang, C.-H.;Huang, C.-C.;Kuan, T.-K.;Liu, S.-I.; Chiang, C.-H.; Huang, C.-C.; Kuan, T.-K.; Liu, S.-I.; SHEN-IUAN LIU
臺大學術典藏 2020-06-11T06:34:48Z A digital MDLL using switched biasing technique to reduce low-frequency phase noise Chiang, C.-H.;Huang, C.-C.;Kuan, T.-K.;Liu, S.-I.; Chiang, C.-H.; Huang, C.-C.; Kuan, T.-K.; Liu, S.-I.; SHEN-IUAN LIU
臺大學術典藏 2020-06-11T06:34:47Z A 0.43pJ/bit true random number generator Kuan, T.-K.;Chiang, Y.-H.;Liu, S.-I.; Kuan, T.-K.; Chiang, Y.-H.; Liu, S.-I.; SHEN-IUAN LIU
臺大學術典藏 2020-06-11T06:34:47Z A 0.43pJ/bit true random number generator Kuan, T.-K.;Chiang, Y.-H.;Liu, S.-I.; Kuan, T.-K.; Chiang, Y.-H.; Liu, S.-I.; SHEN-IUAN LIU

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