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"kuo j b"的相关文件
显示项目 111-128 / 128 (共6页)
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| 國立臺灣大學 |
1991-09 |
A BiCMOS tristate buffer for high-speed microprocessor VLSI
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Kuo, J.B.; Liao, H.J. |
| 國立臺灣大學 |
1991-09 |
Device-level transient analysis of a 1 μm six-transistor BiCMOS inverter circuit using a large-scale quasi-3D device simulator
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Kuo, J.B.; Chen, Y.W. |
| 臺大學術典藏 |
1991-09 |
A BiCMOS tristate buffer for high-speed microprocessor VLSI
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Kuo, J.B.; Liao, H.J.; Kuo, J.B.; Liao, H.J.; KuoJB |
| 臺大學術典藏 |
1991-09 |
Device-level transient analysis of a 1 μm six-transistor BiCMOS inverter circuit using a large-scale quasi-3D device simulator
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Kuo, J.B.; Chen, Y.W.Kuojb; Kuo, J.B.; Chen, Y.W.; KuoJB |
| 國立臺灣大學 |
1991-07 |
BiCMOS edge detector with correlated-double-sampling readout circuit for pattern recognition neural network
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Kuo, J.B.; Chou, T.L.; Wong, E.J. |
| 臺大學術典藏 |
1991-07 |
BiCMOS edge detector with correlated-double-sampling readout circuit for pattern recognition neural network
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Kuo, J.B.; Chou, T.L.; Wong, E.J.; Kuo, J.B.; Chou, T.L.; Wong, E.J.; KuoJB |
| 國立臺灣大學 |
1991-06 |
A structured adaptive neural network for pattern recognition VLSI
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Kuo, J.B.; Wong, E.J.; Chen, C.C.; Hsiao, C.C. |
| 國立臺灣大學 |
1991-06 |
Scaling consideration of BiCMOS SRAMs
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Tsaur, J.J.; Jih, C.W.; Tsaur, H.W.; Kuo, J.B. |
| 國立臺灣大學 |
1991-06 |
A BiCMOS image sensor with a chopper-stabilized edge detector and a correlated-double-sampling readout circuit for pattern recognition neural network VLSI operating at 77 K
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Chou, T.L.; Wong, E.J.; Kuo, J.B. |
| 國立臺灣大學 |
1991-06 |
A one-transistor synapse circuit with an analog LMS adaptive feedback for neural network VLSI
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Lu, T.C.; Chiang, M.L.; Kuo, J.B. |
| 臺大學術典藏 |
1991-06 |
A structured adaptive neural network for pattern recognition VLSI
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Kuo, J.B.; Wong, E.J.; Chen, C.C.; Hsiao, C.C.; Kuo, J.B.; Wong, E.J.; Chen, C.C.; Hsiao, C.C.; KuoJB |
| 國立臺灣大學 |
1991-05 |
Device-level analysis of a 1 μm BiCMOS inverter circuit operating at 77 K using a modified PISCES program
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Kuo, J.B.; Chen, Y.W.; Lou, K.H. |
| 國立臺灣大學 |
1991-05 |
A BiCMOS image sensor with a chopper-stabilized edge detector and a correlated-double-sampling readout circuit for neural network VLSI operating at 77 K
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Chou, T.L.; Wong, E.J.; Lee, W.C.; Kuo, J.B. |
| 國立臺灣大學 |
1991-05 |
A coded block adaptive neural network structure for pattern recognition VLSI
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Kuo, J.B.; Chen, Y.K.; Lu, Y.H.; Mao, W.C. |
| 臺大學術典藏 |
1991-05 |
Device-level analysis of a 1 μm BiCMOS inverter circuit operating at 77 K using a modified PISCES program
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Kuo, J.B.; Chen, Y.W.; Lou, K.H.; Kuo, J.B.; Chen, Y.W.; Lou, K.H.; KuoJB |
| 臺大學術典藏 |
1991-05 |
A coded block adaptive neural network structure for pattern recognition VLSI
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Kuo, J.B.; Chen, Y.K.; Lu, Y.H.; Mao, W.C.; KuoJB; Kuo, J.B.; Chen, Y.K.; Lu, Y.H.; Mao, W.C |
| 國立臺灣大學 |
1990 |
An Improved Analytical Model of Short Channel MOSFETs Suitable for Circuit Simulation
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Chow, H. C.; Wang, J. H.; Kuo, J, B.; 馮武雄; Chow, H. C.; Wang, J. H.; Kuo, J, B.; Feng, Wu-Shiung |
| 國立臺灣大學 |
1989-09 |
Performance analysis of a BiNMOS device
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Kuo, J.B.; Rosseel, G.P.; Dutton, R.W. |
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