臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)

关于TAIR
	计画说明

浏览
	典藏机构
	作者
	题名
	日期
	统计图表
	机构即时统计
	学术趋势

消息
	2019臺灣學術機構典藏研討會
	機構典藏系統RC7版本已發佈

著作权
	出版社及期刊政策查询
	TAIR著作权会议记录

相关连结
	機構典藏計畫網站
	ROAR
	OpenDOAR
	SHERPA
	OAIster
	JAIRO
	Ira
	DSPACE
	RWWR
	臺大學術典藏NTU Scholars

"kuo j b"的相关文件

回到依作者浏览
依题名排序	依日期排序

显示项目 91-128 / 128 (共3页)
<< < 1 2 3 > >>
每页显示[10|25|50]项目

机构	日期	题名	作者
臺大學術典藏	1993-08	Analytical drain current model for a-Si:H TFTs by simultaneously considering localised deep and tail states	Kuo, J.B.; Chen, C.S.; Kuo, J.B.; Chen, C.S.; KuoJB
國立臺灣大學	1993-05	A BiCMOS dynamic divider circuit using a nonrestoring iterative architecture with carry look ahead for CPU VLSI	Kuo, J.B.; Chen, H.P.; Huang, H.J.
國立臺灣大學	1993-05	Accumulation-type vs. inversion-type of an ultra-thin SIO PMOS device operating at 300 K and 77 K: subthreshold behavior and pull-up switching performance of a CMOS inverter	Kuo, J.B.; Sim, J.H.
國立臺灣大學	1993-05	A coded block neural network system suitable for VLSI implementation using an adaptive learning-rate epoch-based back propagation technique	Mao, M.W.; Chen, B.Y.; Kuo, J.B.
臺大學術典藏	1993-05	A BiCMOS dynamic divider circuit using a nonrestoring iterative architecture with carry look ahead for CPU VLSI	Kuo, J.B.; Chen, H.P.; Huang, H.J.; Kuo, J.B.; Chen, H.P.; Huang, H.J.; KuoJB
臺大學術典藏	1993-05	Accumulation-type vs. inversion-type of an ultra-thin SIO PMOS device operating at 300 K and 77 K: subthreshold behavior and pull-up switching performance of a CMOS inverter	Kuo, J.B.; Sim, J.H.; Kuo, J.B.; Sim, J.H.; KuoJB
國立臺灣大學	1993-03	BiCMOS dynamic minimum circuit using a parallel comparison algorithm for fuzzy controllers	Chen, S.S.; Chiang, C.S.; Su, K.W.; Kuo, J.B.
國立臺灣大學	1993	An Improved Analytical Short-Channel MOSFET Model Valid in All Regions of Operation for Analog/Digital Circuit Si[20642:0:4] 50300022:31:An Improved Analytical Short-Channel MOSFET Model Valid in All Regions of Operation for Analog/Digit	Chow, H. C.; 馮武雄; Kuo, J. B.; Chow, H. C.; Feng, Wu-Shiung; Kuo, J. B.
國立臺灣大學	1992-10	Coded block neural network VLSI system using an adaptive learning-rate technique to train Chinese character patterns	Chen, B.Y.; Mao, M.W.; Kuo, J.B.
國立臺灣大學	1992-10	A BiCMOS dynamic full adder circuit for VLSI implementation of high-speed parallel multipliers using Wallace tree reduction architecture	Kuo, J.B.; Liao, H.J.; Chen, H.P.
國立臺灣大學	1992-10	Delayed-turn-on phenomenon in accumulation-type SOI pMOS device operating at liquid nitrogen temperature	Kuo, J.B.; Sim, J.H.
臺大學術典藏	1992-10	A BiCMOS dynamic full adder circuit for VLSI implementation of high-speed parallel multipliers using Wallace tree reduction architecture	Kuo, J.B.; Liao, H.J.; Chen, H.P.; Kuo, J.B.; Liao, H.J.; Chen, H.P.; KuoJB
臺大學術典藏	1992-10	Delayed-turn-on phenomenon in accumulation-type SOI pMOS device operating at liquid nitrogen temperature	Kuo, J.B.; Sim, J.H.; Kuo, J.B.; Sim, J.H.; KuoJB
國立臺灣大學	1992-07	Simple analytical model for short-channel MOS devices	Chow, H.-C.; Feng, W.-S.; Kuo, J.B.
國立臺灣大學	1992-06	BiCMOS dynamic full adder circuit for high-speed parallel multipliers	Chen, H.P.; Liao, H.J.; Kuo, J.B.
國立臺灣大學	1992-06	A radical-partitioned coded block adaptive neural network structure for large-volume Chinese characters recognition	Kuo, J.B.; Mao, M.W.
臺大學術典藏	1992-06	A radical-partitioned coded block adaptive neural network structure for large-volume Chinese characters recognition	Kuo, J.B.; Mao, M.W.; Kuo, J.B.; Mao, M.W.; KuoJB
國立臺灣大學	1992-02	BiCMOS dynamic Manchester carry look ahead circuit for high speed arithmetic unit VLSI	Kuo, J.B.; Liao, H.J.; Chen, H.P.
臺大學術典藏	1992-02	BiCMOS dynamic Manchester carry look ahead circuit for high speed arithmetic unit VLSI	Kuo, J.B.; Liao, H.J.; Chen, H.P.; KuoJB; Kuo, J.B.; Liao, H.J.; Chen, H.P.
國立臺灣大學	1991-12	Analogue adaptive neural network circuit	Chiang, M.L.; Lu, T.C.; Kuo, J.B.
國立臺灣大學	1991-09	A BiCMOS tristate buffer for high-speed microprocessor VLSI	Kuo, J.B.; Liao, H.J.
國立臺灣大學	1991-09	Device-level transient analysis of a 1 μm six-transistor BiCMOS inverter circuit using a large-scale quasi-3D device simulator	Kuo, J.B.; Chen, Y.W.
臺大學術典藏	1991-09	A BiCMOS tristate buffer for high-speed microprocessor VLSI	Kuo, J.B.; Liao, H.J.; Kuo, J.B.; Liao, H.J.; KuoJB
臺大學術典藏	1991-09	Device-level transient analysis of a 1 μm six-transistor BiCMOS inverter circuit using a large-scale quasi-3D device simulator	Kuo, J.B.; Chen, Y.W.Kuojb; Kuo, J.B.; Chen, Y.W.; KuoJB
國立臺灣大學	1991-07	BiCMOS edge detector with correlated-double-sampling readout circuit for pattern recognition neural network	Kuo, J.B.; Chou, T.L.; Wong, E.J.
臺大學術典藏	1991-07	BiCMOS edge detector with correlated-double-sampling readout circuit for pattern recognition neural network	Kuo, J.B.; Chou, T.L.; Wong, E.J.; Kuo, J.B.; Chou, T.L.; Wong, E.J.; KuoJB
國立臺灣大學	1991-06	A structured adaptive neural network for pattern recognition VLSI	Kuo, J.B.; Wong, E.J.; Chen, C.C.; Hsiao, C.C.
國立臺灣大學	1991-06	Scaling consideration of BiCMOS SRAMs	Tsaur, J.J.; Jih, C.W.; Tsaur, H.W.; Kuo, J.B.
國立臺灣大學	1991-06	A BiCMOS image sensor with a chopper-stabilized edge detector and a correlated-double-sampling readout circuit for pattern recognition neural network VLSI operating at 77 K	Chou, T.L.; Wong, E.J.; Kuo, J.B.
國立臺灣大學	1991-06	A one-transistor synapse circuit with an analog LMS adaptive feedback for neural network VLSI	Lu, T.C.; Chiang, M.L.; Kuo, J.B.
臺大學術典藏	1991-06	A structured adaptive neural network for pattern recognition VLSI	Kuo, J.B.; Wong, E.J.; Chen, C.C.; Hsiao, C.C.; Kuo, J.B.; Wong, E.J.; Chen, C.C.; Hsiao, C.C.; KuoJB
國立臺灣大學	1991-05	Device-level analysis of a 1 μm BiCMOS inverter circuit operating at 77 K using a modified PISCES program	Kuo, J.B.; Chen, Y.W.; Lou, K.H.
國立臺灣大學	1991-05	A BiCMOS image sensor with a chopper-stabilized edge detector and a correlated-double-sampling readout circuit for neural network VLSI operating at 77 K	Chou, T.L.; Wong, E.J.; Lee, W.C.; Kuo, J.B.
國立臺灣大學	1991-05	A coded block adaptive neural network structure for pattern recognition VLSI	Kuo, J.B.; Chen, Y.K.; Lu, Y.H.; Mao, W.C.
臺大學術典藏	1991-05	Device-level analysis of a 1 μm BiCMOS inverter circuit operating at 77 K using a modified PISCES program	Kuo, J.B.; Chen, Y.W.; Lou, K.H.; Kuo, J.B.; Chen, Y.W.; Lou, K.H.; KuoJB
臺大學術典藏	1991-05	A coded block adaptive neural network structure for pattern recognition VLSI	Kuo, J.B.; Chen, Y.K.; Lu, Y.H.; Mao, W.C.; KuoJB; Kuo, J.B.; Chen, Y.K.; Lu, Y.H.; Mao, W.C
國立臺灣大學	1990	An Improved Analytical Model of Short Channel MOSFETs Suitable for Circuit Simulation	Chow, H. C.; Wang, J. H.; Kuo, J, B.; 馮武雄; Chow, H. C.; Wang, J. H.; Kuo, J, B.; Feng, Wu-Shiung
國立臺灣大學	1989-09	Performance analysis of a BiNMOS device	Kuo, J.B.; Rosseel, G.P.; Dutton, R.W.

显示项目 91-128 / 128 (共3页)
<< < 1 2 3 > >>
每页显示[10|25|50]项目

	English \| 正體中文 \| 简体中文 \| 总笔数 :2822924
	造访人次 : 30049965 在线人数 : 1049 教育部委托研究计画计画执行:国立台湾大学图书馆