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機構	日期	題名	作者
臺大學術典藏	2021-09-02T00:05:24Z	Modeling power vertical high-k MOS device with interface charges via superposition methodology-breakdown voltage and specific ON-resistance	Wang Z;Wang X;Kuo J.B.; Wang Z; Wang X; Kuo J.B.; JAMES-B KUO
臺大學術典藏	2021-09-02T00:05:24Z	On the form of 1-D nonlinear Poisson’s equation and the concept of neutralization voltage for non-uniformly doped MOSFETs	Hong C;Kuo J.B;Chen Y.; Hong C; Kuo J.B; Chen Y.; JAMES-B KUO
臺大學術典藏	2021-09-02T00:05:23Z	A Substrate-Dissipating (SD) Mechanism for a Ruggedness-Improved SOI LDMOS Device	Wang B;Wang Z;Kuo J.B.; Wang B; Wang Z; Kuo J.B.; JAMES-B KUO
臺大學術典藏	2021-09-02T00:05:23Z	A Unified Continuous and Discrete Model for Double-Gate MOSFETs with Spatially Varying or Pulsed Doping Profiles	Hong C;Zhou J;Cheng Q;Zhu K;Kuo J.B;Chen Y.; Hong C; Zhou J; Cheng Q; Zhu K; Kuo J.B; Chen Y.; JAMES-B KUO
臺大學術典藏	2021-09-02T00:05:23Z	Author's Reply to "comments on 'A General and Transformable Model Platform for Emerging Multi-Gate MOSFETs'"	Hong C;Zhou J;Wang R;Huang J;Bai W;Kuo J.B;Chen Y.; Hong C; Zhou J; Wang R; Huang J; Bai W; Kuo J.B; Chen Y.; JAMES-B KUO
臺大學術典藏	2021-09-02T00:05:23Z	Modeling of Breakdown Voltage for SOI Trench LDMOS Device Based on Conformal Mapping	Wang Y;Wang Z;Bai T;Kuo J.B.; Wang Y; Wang Z; Bai T; Kuo J.B.; JAMES-B KUO
臺大學術典藏	2021-09-02T00:05:22Z	A General and Transformable Model Platform for Emerging Multi-Gate MOSFETs	Hong C;Zhou J;Huang J;Wang R;Bai W;Kuo J.B;Chen Y.; Hong C; Zhou J; Huang J; Wang R; Bai W; Kuo J.B; Chen Y.; JAMES-B KUO
臺大學術典藏	2018-09-10T05:18:26Z	A hierarchical and multi-model based algorithm for lead detection and news program narrative parsing	Kuo, J.-H.; Kuo, J.-B.; Chen, H.-W.; Wu, J.-L.; JA-LING WU
國立臺灣大學	2010	Shallow Trench Isolation-Related Narrow Channel Effect on the Kink Effect Behavior of 40nm PD SOI NMOS Device	Hung, H. J.; Kuo, J. B.; Chen, D.; Tsai, C. T.; Yeh, C. S.
臺大學術典藏	2010	Modeling the parasitic bipolar device in the 40nm PD SOI NMOS device considering the floating body effect	CHIH-HAO CHEN; Kuo J.B.; Chen D.; Yeh C.S.
國立臺灣大學	2009	Closed-Form Partitioned Gate Tunneling Current Model for NMOS Devices with an Ultra-thin Gate Oxide	Lin, C.H.; Kuo, J.B.
國立臺灣大學	2008	Gate-Level Dual-Threshold Static Power Optimization Methodology (GDSPOM) Using Path-Based Static Timing Analysis (STA) Technique for SOC Application	Chung, B.; Kuo, J.B.
國立臺灣大學	2008	Breakdown Behavior of 40-nm PD-SOI NMOS Device Considering STI-Induced Mechanical Stress Effect	Su, V.C.; Lin, I.S.; Kuo, J.B.; Lin, G.S.; Chen, D.; Yeh, C.S.; Tsai, C.T.; Ma, M.
國立臺灣大學	2007	Narrow Band Gap Semiconductor	Lin, H. H.; Kuo, J. B.
國立臺灣大學	2007	Narrow Bandgap Semiconductor	Lin, H. H.; Kuo, J. B.
國立臺灣大學	2006-02	Partitioned gate tunnelling current model considering distributed effect for CMOS devices with ultra-thin (1 nm) gate oxide	Lin, C.H.; Kuo, J.B.; Su, K.W.; Liu, S.
國立臺灣大學	2006	Gate capacitances behavior of nanometer FD SOI CMOS devices with HfO2 high-k gate dielectric considering vertical and fringing displacement effects using 2-D Simulation	Lin, Yu-Sheng; Lin, Chia-Hong; Kuo, J.B.; Su, Ke-Wei
國立臺灣大學	2006	Analysis of the gate-source/drain capacitance behavior of a narrow-channel FD SOI NMOS device considering the 3-D fringing capacitances using 3-D simulation	Chen, Chien-Chung; Kuo, J.B.; Su, Ke-Wei; Liu, Sally
國立臺灣大學	2005-05	Energy-efficient CMOS large-load driver circuit with the complementary adiabatic/bootstrap (CAB) technique for low-power TFT-LCD system applications	Liu, G.Y.; Wang, N.C.; Kuo, J.B.
臺大學術典藏	2005-05	Energy-efficient CMOS large-load driver circuit with the complementary adiabatic/bootstrap (CAB) technique for low-power TFT-LCD system applications	Liu, G.Y.; Wang, N.C.; Kuo, J.B.; Liu, G.Y.; Wang, N.C.; Kuo, J.B.
國立臺灣大學	2005-04	0.7 V Manchester carry look-ahead circuit using PD SOI CMOS asymmetrical dynamic threshold pass transistor techniques suitable for low-voltage CMOS VLSI systems	Chiang, T.Y.; Kuo, J.B.
國立臺灣大學	2004-12	A 0.8 V CMOS TSPC adiabatic DCVS logic circuit with the bootstrap technique for low-power VLSI	Chen, H.P.; Kuo, J.B.
國立臺灣大學	2004-07	Evolution of low-voltage CMOS digital VLSI circuits using bootstrap technique	Kuo, J.B.
臺大學術典藏	2004-07	Evolution of low-voltage CMOS digital VLSI circuits using bootstrap technique	Kuo, J.B.Kuojb; Kuo, J.B.; KuoJB
國立臺灣大學	2004-04	Low-Voltage SOI CMOS VLSI Devices and Circuits	Lin, S. C.; Kuo, J. B.
國立臺灣大學	2004-03	CMOS Digital IC	Kuo, J. B.
國立臺灣大學	2004	A Compact Threshold Voltage Model for Gate Misalignment Effect of DG FD SOI NMOS Devices Considering Fringing Electric Field Effects	Kuo, J.B.; Sun, E.C.
國立臺灣大學	2003-11	Analysis of gate misalignment effect on the threshold voltage of double-gate (DG) ultrathin fully-depleted (FD) silicon-on-insulator (SOI) NMOS devices using a compact model considering fringing electric field effect	Kuo, J.B.; Sun, E.C.; Lin, M.T.
臺大學術典藏	2003-11	Analysis of gate misalignment effect on the threshold voltage of double-gate (DG) ultrathin fully-depleted (FD) silicon-on-insulator (SOI) NMOS devices using a compact model considering fringing electric field effect	Kuo, J.B.; Sun, E.C.; Lin, M.T.Kuojb; Kuo, J.B.; Sun, E.C.; Lin, M.T.; KuoJB
國立臺灣大學	2003	Ultra-Low-Voltage SOI CMOS Inverting Driver Circuit Using Effective Charge Pump Based on Bootstrap Technique	Chen, J.H.T.; Kuo, J.B.
國立臺灣大學	2003	Modeling the Fringing Electric Field Effect on the Threshold Voltage of FD SOI NMOS Devices with the LDD/Sidewall Oxide Spacer Structure	Lin, S.C.; Kuo, J.B.
國立臺灣大學	2002-03-14	Sub-I V CMOS large capacitive-load driver circuit using direct bootstrap technique for ' low-voltage CMOS VLSI	Chen, P.C.; Kuo, J.B.
國立臺灣大學	2002	Compact threshold-voltage model for short-channelpartially-depleted (PD) SOI dynamic-threshold MOS (DTMOS) devices	Kuo, J.B.; Yuan, Kuo-Hua; Lin, Shih-Chia
國立臺灣大學	2002	Sub-1 V CMOS large capacitive-load driver circuit using directbootstrap technique for low-voltage CMOS VLSI	Chen, P.C.; Kuo, J.B.
國立臺灣大學	2002	A 0.8-V 128-Kb Four-Way Set-Associative Two-Level CMOS Cache Memory Using Two-Stage Wordline/Bitline-Oriented Tag-Compare (WLOTC/BLOTC) Scheme	Lin, Perng-Fei; Kuo, J.B.
國立臺灣大學	2002	0.8V CMOS Adiabatic Differential Switch Logic Circuit Using Bootstrap Technique for Low-Voltage Low-Power VLSI	Zhang, Y.; Chen, H.H.; Kuo, J.B.
國立臺灣大學	2002	Closed-Form Breakdown Voltage Model for PD SOI NMOS Devices Considering Impact Ionization of Both Parasitic BJT and Surface MOS Channel Simultaneously	Lin, Shih-Chia; Kuo, J.B.
國立臺灣大學	2002	Closed-form analytical drain current model considering energy transport and self-heating for short-channel fully-depleted SOI NMOS devices with lightly-doped drain structure biased in strong inversion	Lin, Shih-Chia; Kuo, J.B.
國立臺灣大學	2001	A Novel Low-Voltage Content-Addressable-Memory (CAM) Cell with a Fast Tag-Compare Capability using Partially-Depleted (PD) SOI CMOS Dynamic-Threshold (DTMOS) Techniques	Liu, S.C.; Wu, F.A.; Kuo, J.B.
國立臺灣大學	2001	A 1-V 128-kb four-way set-associative CMOS cache memory usingwordline-oriented tag-compare (WLOTC) structure with thecontent-addressable-memory (CAM) 10-transistor tag cell	Lin, Perng-Fei; Kuo, J.B.
國立臺灣大學	2000-08	A novel low-voltage silicon-on-insulator (SOI) CMOS complementary pass-transistor logic (CPL) circuit using asymmetrical dynamic threshold pass-transistor (ADTPT) technique	Wang, Bo-Ting; Kuo, J.B.
國立臺灣大學	2000-06	Short-channel effects of SOI partially-depleted (PD) dynamic-threshold MOS (DTMOS) devices	Lin, S.C.; Yuan, K.H.; Kuo, J.B.
國立臺灣大學	2000-06	SPICE compact modeling of PD-SOI CMOS devices	Kuo, J.B.
臺大學術典藏	2000-06	SPICE compact modeling of PD-SOI CMOS devices	Kuo, J.B.; Kuo, J.B.; KuoJB
國立臺灣大學	2000-05	A novel two-port 6T CMOS SRAM cell structure for low-voltage VLSI SRAM with single-bit-line simultaneous read-and-write access (SBLSRWA) capability	Wang, B.T.; Kuo, J.B.
國立臺灣大學	2000	A Closed-Form Back-Gate-Bias Related Inverse Narrow-Channel Effect Model for Deep-Submicron VLSI CMOS Devices Using Shallow Trench Isolation	Lin, Shih-Chia; Kuo, J.B.; Huang, Kuo-Tai; Sun, Shih-Wei
國立臺灣大學	2000	A High-Speed Conditional Carry Select (CCS) Adder Circuit with a Successively Incremented Carry Number Block (SICNB) Structure for Low-Voltage VLSI Implementation	Huang, Yen-Mou; Kuo, J.B.
國立臺灣大學	1999-10	A novel 0.7 V two-port 6T SRAM memory cell structure with single-bit-line simultaneous read-and-write access (SBLSRWA) capability using partially-depleted SOI CMOS dynamic-threshold technique	Liu, S.C.; Kuo, J.B.
國立臺灣大學	1999	Temperature-dependent kink effect model for partially-depleted SOINMOS devices	Lin, S.C.; Kuo, J.B.
國立臺灣大學	1999	A 1.5-V CMOS all-N-logic true-single-phase bootstrappeddynamic-logic circuit suitable for low supply voltage and high-speedpipelined system operation	Lou, J.H.; Kuo, J.B.

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