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教育部委託研究計畫 計畫執行:國立臺灣大學圖書館
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"kuo j b"的相關文件
顯示項目 41-50 / 128 (共13頁)
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| 國立臺灣大學 |
2000-08 |
A novel low-voltage silicon-on-insulator (SOI) CMOS complementary pass-transistor logic (CPL) circuit using asymmetrical dynamic threshold pass-transistor (ADTPT) technique
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Wang, Bo-Ting; Kuo, J.B. |
| 國立臺灣大學 |
2000-06 |
Short-channel effects of SOI partially-depleted (PD) dynamic-threshold MOS (DTMOS) devices
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Lin, S.C.; Yuan, K.H.; Kuo, J.B. |
| 國立臺灣大學 |
2000-06 |
SPICE compact modeling of PD-SOI CMOS devices
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Kuo, J.B. |
| 臺大學術典藏 |
2000-06 |
SPICE compact modeling of PD-SOI CMOS devices
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Kuo, J.B.; Kuo, J.B.; KuoJB |
| 國立臺灣大學 |
2000-05 |
A novel two-port 6T CMOS SRAM cell structure for low-voltage VLSI SRAM with single-bit-line simultaneous read-and-write access (SBLSRWA) capability
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Wang, B.T.; Kuo, J.B. |
| 國立臺灣大學 |
2000 |
A Closed-Form Back-Gate-Bias Related Inverse Narrow-Channel Effect Model for Deep-Submicron VLSI CMOS Devices Using Shallow Trench Isolation
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Lin, Shih-Chia; Kuo, J.B.; Huang, Kuo-Tai; Sun, Shih-Wei |
| 國立臺灣大學 |
2000 |
A High-Speed Conditional Carry Select (CCS) Adder Circuit with a Successively Incremented Carry Number Block (SICNB) Structure for Low-Voltage VLSI Implementation
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Huang, Yen-Mou; Kuo, J.B. |
| 國立臺灣大學 |
1999-10 |
A novel 0.7 V two-port 6T SRAM memory cell structure with single-bit-line simultaneous read-and-write access (SBLSRWA) capability using partially-depleted SOI CMOS dynamic-threshold technique
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Liu, S.C.; Kuo, J.B. |
| 國立臺灣大學 |
1999 |
Temperature-dependent kink effect model for partially-depleted SOINMOS devices
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Lin, S.C.; Kuo, J.B. |
| 國立臺灣大學 |
1999 |
A 1.5-V CMOS all-N-logic true-single-phase bootstrappeddynamic-logic circuit suitable for low supply voltage and high-speedpipelined system operation
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Lou, J.H.; Kuo, J.B. |
顯示項目 41-50 / 128 (共13頁)
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