| 臺大學術典藏 |
2021-09-02T00:05:24Z |
Modeling power vertical high-k MOS device with interface charges via superposition methodology-breakdown voltage and specific ON-resistance
|
Wang Z;Wang X;Kuo J.B.; Wang Z; Wang X; Kuo J.B.; JAMES-B KUO |
| 臺大學術典藏 |
2021-09-02T00:05:24Z |
On the form of 1-D nonlinear Poisson’s equation and the concept of neutralization voltage for non-uniformly doped MOSFETs
|
Hong C;Kuo J.B;Chen Y.; Hong C; Kuo J.B; Chen Y.; JAMES-B KUO |
| 臺大學術典藏 |
2021-09-02T00:05:23Z |
A Substrate-Dissipating (SD) Mechanism for a Ruggedness-Improved SOI LDMOS Device
|
Wang B;Wang Z;Kuo J.B.; Wang B; Wang Z; Kuo J.B.; JAMES-B KUO |
| 臺大學術典藏 |
2021-09-02T00:05:23Z |
A Unified Continuous and Discrete Model for Double-Gate MOSFETs with Spatially Varying or Pulsed Doping Profiles
|
Hong C;Zhou J;Cheng Q;Zhu K;Kuo J.B;Chen Y.; Hong C; Zhou J; Cheng Q; Zhu K; Kuo J.B; Chen Y.; JAMES-B KUO |
| 臺大學術典藏 |
2021-09-02T00:05:23Z |
Author's Reply to "comments on 'A General and Transformable Model Platform for Emerging Multi-Gate MOSFETs'"
|
Hong C;Zhou J;Wang R;Huang J;Bai W;Kuo J.B;Chen Y.; Hong C; Zhou J; Wang R; Huang J; Bai W; Kuo J.B; Chen Y.; JAMES-B KUO |
| 臺大學術典藏 |
2021-09-02T00:05:23Z |
Modeling of Breakdown Voltage for SOI Trench LDMOS Device Based on Conformal Mapping
|
Wang Y;Wang Z;Bai T;Kuo J.B.; Wang Y; Wang Z; Bai T; Kuo J.B.; JAMES-B KUO |
| 臺大學術典藏 |
2021-09-02T00:05:22Z |
A General and Transformable Model Platform for Emerging Multi-Gate MOSFETs
|
Hong C;Zhou J;Huang J;Wang R;Bai W;Kuo J.B;Chen Y.; Hong C; Zhou J; Huang J; Wang R; Bai W; Kuo J.B; Chen Y.; JAMES-B KUO |
| 臺大學術典藏 |
2018-09-10T05:18:26Z |
A hierarchical and multi-model based algorithm for lead detection and news program narrative parsing
|
Kuo, J.-H.; Kuo, J.-B.; Chen, H.-W.; Wu, J.-L.; JA-LING WU |
| 國立臺灣大學 |
2010 |
Shallow Trench Isolation-Related Narrow Channel Effect on the Kink Effect Behavior of 40nm PD SOI NMOS Device
|
Hung, H. J.; Kuo, J. B.; Chen, D.; Tsai, C. T.; Yeh, C. S. |
| 臺大學術典藏 |
2010 |
Modeling the parasitic bipolar device in the 40nm PD SOI NMOS device considering the floating body effect
|
CHIH-HAO CHEN; Kuo J.B.; Chen D.; Yeh C.S. |
| 國立臺灣大學 |
2009 |
Closed-Form Partitioned Gate Tunneling Current Model for NMOS Devices with an Ultra-thin Gate Oxide
|
Lin, C.H.; Kuo, J.B. |
| 國立臺灣大學 |
2008 |
Gate-Level Dual-Threshold Static Power Optimization Methodology (GDSPOM) Using Path-Based Static Timing Analysis (STA) Technique for SOC Application
|
Chung, B.; Kuo, J.B. |
| 國立臺灣大學 |
2008 |
Breakdown Behavior of 40-nm PD-SOI NMOS Device Considering STI-Induced Mechanical Stress Effect
|
Su, V.C.; Lin, I.S.; Kuo, J.B.; Lin, G.S.; Chen, D.; Yeh, C.S.; Tsai, C.T.; Ma, M. |
| 國立臺灣大學 |
2007 |
Narrow Band Gap Semiconductor
|
Lin, H. H.; Kuo, J. B. |
| 國立臺灣大學 |
2007 |
Narrow Bandgap Semiconductor
|
Lin, H. H.; Kuo, J. B. |
| 國立臺灣大學 |
2006-02 |
Partitioned gate tunnelling current model considering distributed effect for CMOS devices with ultra-thin (1 nm) gate oxide
|
Lin, C.H.; Kuo, J.B.; Su, K.W.; Liu, S. |
| 國立臺灣大學 |
2006 |
Gate capacitances behavior of nanometer FD SOI CMOS devices with HfO2 high-k gate dielectric considering vertical and fringing displacement effects using 2-D Simulation
|
Lin, Yu-Sheng; Lin, Chia-Hong; Kuo, J.B.; Su, Ke-Wei |
| 國立臺灣大學 |
2006 |
Analysis of the gate-source/drain capacitance behavior of a narrow-channel FD SOI NMOS device considering the 3-D fringing capacitances using 3-D simulation
|
Chen, Chien-Chung; Kuo, J.B.; Su, Ke-Wei; Liu, Sally |
| 國立臺灣大學 |
2005-05 |
Energy-efficient CMOS large-load driver circuit with the complementary adiabatic/bootstrap (CAB) technique for low-power TFT-LCD system applications
|
Liu, G.Y.; Wang, N.C.; Kuo, J.B. |
| 臺大學術典藏 |
2005-05 |
Energy-efficient CMOS large-load driver circuit with the complementary adiabatic/bootstrap (CAB) technique for low-power TFT-LCD system applications
|
Liu, G.Y.; Wang, N.C.; Kuo, J.B.; Liu, G.Y.; Wang, N.C.; Kuo, J.B. |
| 國立臺灣大學 |
2005-04 |
0.7 V Manchester carry look-ahead circuit using PD SOI CMOS asymmetrical dynamic threshold pass transistor techniques suitable for low-voltage CMOS VLSI systems
|
Chiang, T.Y.; Kuo, J.B. |
| 國立臺灣大學 |
2004-12 |
A 0.8 V CMOS TSPC adiabatic DCVS logic circuit with the bootstrap technique for low-power VLSI
|
Chen, H.P.; Kuo, J.B. |
| 國立臺灣大學 |
2004-07 |
Evolution of low-voltage CMOS digital VLSI circuits using bootstrap technique
|
Kuo, J.B. |
| 臺大學術典藏 |
2004-07 |
Evolution of low-voltage CMOS digital VLSI circuits using bootstrap technique
|
Kuo, J.B.Kuojb; Kuo, J.B.; KuoJB |
| 國立臺灣大學 |
2004-04 |
Low-Voltage SOI CMOS VLSI Devices and Circuits
|
Lin, S. C.; Kuo, J. B. |
