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Showing items 26-50 of 128 (6 Page(s) Totally) << < 1 2 3 4 5 6 > >> View [10|25|50] records per page
國立臺灣大學 |
2004-03 |
CMOS Digital IC
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Kuo, J. B. |
國立臺灣大學 |
2004 |
A Compact Threshold Voltage Model for Gate Misalignment Effect of DG FD SOI NMOS Devices Considering Fringing Electric Field Effects
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Kuo, J.B.; Sun, E.C. |
國立臺灣大學 |
2003-11 |
Analysis of gate misalignment effect on the threshold voltage of double-gate (DG) ultrathin fully-depleted (FD) silicon-on-insulator (SOI) NMOS devices using a compact model considering fringing electric field effect
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Kuo, J.B.; Sun, E.C.; Lin, M.T. |
臺大學術典藏 |
2003-11 |
Analysis of gate misalignment effect on the threshold voltage of double-gate (DG) ultrathin fully-depleted (FD) silicon-on-insulator (SOI) NMOS devices using a compact model considering fringing electric field effect
|
Kuo, J.B.; Sun, E.C.; Lin, M.T.Kuojb; Kuo, J.B.; Sun, E.C.; Lin, M.T.; KuoJB |
國立臺灣大學 |
2003 |
Ultra-Low-Voltage SOI CMOS Inverting Driver Circuit Using Effective Charge Pump Based on Bootstrap Technique
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Chen, J.H.T.; Kuo, J.B. |
國立臺灣大學 |
2003 |
Modeling the Fringing Electric Field Effect on the Threshold Voltage of FD SOI NMOS Devices with the LDD/Sidewall Oxide Spacer Structure
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Lin, S.C.; Kuo, J.B. |
國立臺灣大學 |
2002-03-14 |
Sub-I V CMOS large capacitive-load driver circuit using direct bootstrap technique for ' low-voltage CMOS VLSI
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Chen, P.C.; Kuo, J.B. |
國立臺灣大學 |
2002 |
Compact threshold-voltage model for short-channelpartially-depleted (PD) SOI dynamic-threshold MOS (DTMOS) devices
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Kuo, J.B.; Yuan, Kuo-Hua; Lin, Shih-Chia |
國立臺灣大學 |
2002 |
Sub-1 V CMOS large capacitive-load driver circuit using directbootstrap technique for low-voltage CMOS VLSI
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Chen, P.C.; Kuo, J.B. |
國立臺灣大學 |
2002 |
A 0.8-V 128-Kb Four-Way Set-Associative Two-Level CMOS Cache Memory Using Two-Stage Wordline/Bitline-Oriented Tag-Compare (WLOTC/BLOTC) Scheme
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Lin, Perng-Fei; Kuo, J.B. |
國立臺灣大學 |
2002 |
0.8V CMOS Adiabatic Differential Switch Logic Circuit Using Bootstrap Technique for Low-Voltage Low-Power VLSI
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Zhang, Y.; Chen, H.H.; Kuo, J.B. |
國立臺灣大學 |
2002 |
Closed-Form Breakdown Voltage Model for PD SOI NMOS Devices Considering Impact Ionization of Both Parasitic BJT and Surface MOS Channel Simultaneously
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Lin, Shih-Chia; Kuo, J.B. |
國立臺灣大學 |
2002 |
Closed-form analytical drain current model considering energy transport and self-heating for short-channel fully-depleted SOI NMOS devices with lightly-doped drain structure biased in strong inversion
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Lin, Shih-Chia; Kuo, J.B. |
國立臺灣大學 |
2001 |
A Novel Low-Voltage Content-Addressable-Memory (CAM) Cell with a Fast Tag-Compare Capability using Partially-Depleted (PD) SOI CMOS Dynamic-Threshold (DTMOS) Techniques
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Liu, S.C.; Wu, F.A.; Kuo, J.B. |
國立臺灣大學 |
2001 |
A 1-V 128-kb four-way set-associative CMOS cache memory usingwordline-oriented tag-compare (WLOTC) structure with thecontent-addressable-memory (CAM) 10-transistor tag cell
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Lin, Perng-Fei; Kuo, J.B. |
國立臺灣大學 |
2000-08 |
A novel low-voltage silicon-on-insulator (SOI) CMOS complementary pass-transistor logic (CPL) circuit using asymmetrical dynamic threshold pass-transistor (ADTPT) technique
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Wang, Bo-Ting; Kuo, J.B. |
國立臺灣大學 |
2000-06 |
Short-channel effects of SOI partially-depleted (PD) dynamic-threshold MOS (DTMOS) devices
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Lin, S.C.; Yuan, K.H.; Kuo, J.B. |
國立臺灣大學 |
2000-06 |
SPICE compact modeling of PD-SOI CMOS devices
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Kuo, J.B. |
臺大學術典藏 |
2000-06 |
SPICE compact modeling of PD-SOI CMOS devices
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Kuo, J.B.; Kuo, J.B.; KuoJB |
國立臺灣大學 |
2000-05 |
A novel two-port 6T CMOS SRAM cell structure for low-voltage VLSI SRAM with single-bit-line simultaneous read-and-write access (SBLSRWA) capability
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Wang, B.T.; Kuo, J.B. |
國立臺灣大學 |
2000 |
A Closed-Form Back-Gate-Bias Related Inverse Narrow-Channel Effect Model for Deep-Submicron VLSI CMOS Devices Using Shallow Trench Isolation
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Lin, Shih-Chia; Kuo, J.B.; Huang, Kuo-Tai; Sun, Shih-Wei |
國立臺灣大學 |
2000 |
A High-Speed Conditional Carry Select (CCS) Adder Circuit with a Successively Incremented Carry Number Block (SICNB) Structure for Low-Voltage VLSI Implementation
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Huang, Yen-Mou; Kuo, J.B. |
國立臺灣大學 |
1999-10 |
A novel 0.7 V two-port 6T SRAM memory cell structure with single-bit-line simultaneous read-and-write access (SBLSRWA) capability using partially-depleted SOI CMOS dynamic-threshold technique
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Liu, S.C.; Kuo, J.B. |
國立臺灣大學 |
1999 |
Temperature-dependent kink effect model for partially-depleted SOINMOS devices
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Lin, S.C.; Kuo, J.B. |
國立臺灣大學 |
1999 |
A 1.5-V CMOS all-N-logic true-single-phase bootstrappeddynamic-logic circuit suitable for low supply voltage and high-speedpipelined system operation
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Lou, J.H.; Kuo, J.B. |
Showing items 26-50 of 128 (6 Page(s) Totally) << < 1 2 3 4 5 6 > >> View [10|25|50] records per page
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