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Showing items 46-55 of 128 (13 Page(s) Totally)
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| 國立臺灣大學 |
2000 |
A Closed-Form Back-Gate-Bias Related Inverse Narrow-Channel Effect Model for Deep-Submicron VLSI CMOS Devices Using Shallow Trench Isolation
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Lin, Shih-Chia; Kuo, J.B.; Huang, Kuo-Tai; Sun, Shih-Wei |
| 國立臺灣大學 |
2000 |
A High-Speed Conditional Carry Select (CCS) Adder Circuit with a Successively Incremented Carry Number Block (SICNB) Structure for Low-Voltage VLSI Implementation
|
Huang, Yen-Mou; Kuo, J.B. |
| 國立臺灣大學 |
1999-10 |
A novel 0.7 V two-port 6T SRAM memory cell structure with single-bit-line simultaneous read-and-write access (SBLSRWA) capability using partially-depleted SOI CMOS dynamic-threshold technique
|
Liu, S.C.; Kuo, J.B. |
| 國立臺灣大學 |
1999 |
Temperature-dependent kink effect model for partially-depleted SOINMOS devices
|
Lin, S.C.; Kuo, J.B. |
| 國立臺灣大學 |
1999 |
A 1.5-V CMOS all-N-logic true-single-phase bootstrappeddynamic-logic circuit suitable for low supply voltage and high-speedpipelined system operation
|
Lou, J.H.; Kuo, J.B. |
| 國立臺灣大學 |
1999 |
Bandgap Narrowing
|
Kuo, J. B. |
| 國立臺灣大學 |
1999 |
A CMOS Semi-Static Latch Circuit without Charge Sharing and Leakage Current Problems
|
Lin, P. F.; Kuo, J. B. |
| 國立臺灣大學 |
1999 |
A Low-Voltage Semi-Dynamic DCVSPG-Domino Logic Circuit
|
Lou, J. H.; Kuo, J. B. |
| 國立臺灣大學 |
1999 |
Modeling of Deep-Submicron SOI CMOS VLSI Devices
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Kuo, J. B. |
| 國立臺灣大學 |
1998-09 |
1.5 V CMOS bootstrapped dynamic logic circuit techniques (BDLCT) suitable for low-voltage deep-submicron CMOS VLSI for implementing 482 MHz digital quadrature modulator and adder
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Lou, J.H.; Kuo, J.B. |
Showing items 46-55 of 128 (13 Page(s) Totally)
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