|
Taiwan Academic Institutional Repository >
Browse by Author
|
"kuo j b"
Showing items 51-100 of 128 (3 Page(s) Totally) << < 1 2 3 > >> View [10|25|50] records per page
國立臺灣大學 |
1999 |
Bandgap Narrowing
|
Kuo, J. B. |
國立臺灣大學 |
1999 |
A CMOS Semi-Static Latch Circuit without Charge Sharing and Leakage Current Problems
|
Lin, P. F.; Kuo, J. B. |
國立臺灣大學 |
1999 |
A Low-Voltage Semi-Dynamic DCVSPG-Domino Logic Circuit
|
Lou, J. H.; Kuo, J. B. |
國立臺灣大學 |
1999 |
Modeling of Deep-Submicron SOI CMOS VLSI Devices
|
Kuo, J. B. |
國立臺灣大學 |
1998-09 |
1.5 V CMOS bootstrapped dynamic logic circuit techniques (BDLCT) suitable for low-voltage deep-submicron CMOS VLSI for implementing 482 MHz digital quadrature modulator and adder
|
Lou, J.H.; Kuo, J.B. |
國立臺灣大學 |
1997-10 |
Compact current model for mesa-isolated fully-depleted ultrathin SOI NMOS devices considering sidewall-related narrow channel effects
|
Kuo, J.B.; Su, K.W. |
臺大學術典藏 |
1997-10 |
Compact current model for mesa-isolated fully-depleted ultrathin SOI NMOS devices considering sidewall-related narrow channel effects
|
Kuo, J.B.; Su, K.W.; Kuo, J.B.; Su, K.W.; KuoJB |
國立臺灣大學 |
1997-08 |
A 1.5 V CMOS high-speed 16-bit÷8-bit divider using the quotient-select architecture and true-single-phase bootstrapped dynamic circuit techniques suitable for low-voltage VLSI
|
Yeh, C.C.; Lou, J.H.; Kuo, J.B. |
國立臺灣大學 |
1997-08 |
A 1.5 V bootstrapped pass-transistor-based carry look-ahead circuit suitable for low-voltage CMOS VLSI
|
Lou, J.H.; Kuo, J.B. |
國立臺灣大學 |
1997-07 |
1.5 V CMOS full-swing energy efficient logic (EEL) circuit suitable for low-voltage and low-power VLSI applications
|
Yeh, C.C.; Lou, J.H.; Kuo, J.B. |
國立臺灣大學 |
1996-09 |
Analytical current conduction model for accumulation-mode SOI PMOS devices
|
Su, K.W.; Kuo, J.B. |
國立臺灣大學 |
1996 |
A velocity-overshoot capacitance model for 0.1 μm MOS transistors
|
Kuo, J. B.; Chang, Y. W.; Lai, C. S. |
國立臺灣大學 |
1995-10 |
SiC vs. Si: two-dimensional analysis of quasi-saturation behavior of DMOS devices operating at elevated temperatures
|
Chang, Y.W.; Kuo, J.B. |
國立臺灣大學 |
1995-10 |
An analytical delayed-turn-off model for 6H-SiC buried-channel NMOS devices considering incomplete ionization
|
Su, K.W.; Kuo, J.B. |
國立臺灣大學 |
1995-10 |
Accumulation-type vs. inversion-type: narrow channel effect in VLSI mesa-isolated fully-depleted ultra-thin SOI PMOS devices
|
Su, K.W.; Kuo, J.B. |
國立臺灣大學 |
1995-09 |
A high-speed 1.5 V clocked BiCMOS latch for BiCMOS dynamic pipelined digital logic VLSI systems
|
Kuo, J.B.; Lou, J.H.; Su, K.W. |
臺大學術典藏 |
1995-09 |
A high-speed 1.5 V clocked BiCMOS latch for BiCMOS dynamic pipelined digital logic VLSI systems
|
Kuo, J.B.; Lou, J.H.; Su, K.W.; Kuo, J.B.; Lou, J.H.; Su, K.W.; KuoJB |
國立臺灣大學 |
1995-05 |
A closed-form physical back-gate-bias dependent quasi-saturation model for SOI lateral DMOS devices with self-heating for circuit simulation
|
Liu, C.M.; Shone, F.C.; Kuo, J.B. |
國立臺灣大學 |
1994-12 |
A 1.5 V 10 MHz BiCMOS quasi-digital vector modulator for wireless communication IC
|
Su, K.W.; Chen, Y.G.; Lai, C.S.; Kuo, J.B.; Wu, J.S.; Tso, H.W. |
國立臺灣大學 |
1994-10 |
Back gate bias dependent quasi-saturation in a high-voltage SOI MOSFET: 2D analysis and closed-form analytical model
|
Liu, C.M.; Kuo, J.B. |
國立臺灣大學 |
1994-08 |
A 1.5 V BiCMOS dynamic subtracter circuit for low-voltage BiCMOS CPU VLSI
|
Chen, Y.G.; Kuo, J.B. |
國立臺灣大學 |
1994-07 |
A radical-partitioned neural network system using a modified Sigmoid function and a weight-dotted radical selector for large-volume Chinese characters recognition VLSI
|
Kuo, J.B.; Chen, B.Y.; Mao, M.W. |
臺大學術典藏 |
1994-07 |
A radical-partitioned neural network system using a modified Sigmoid function and a weight-dotted radical selector for large-volume Chinese characters recognition VLSI
|
Kuo, J.B.; Chen, B.Y.; Mao, M.W.; Kuo, J.B.; Chen, B.Y.; Mao, M.W.; KuoJB |
國立臺灣大學 |
1994-06 |
A BiCMOS dynamic multiplier using Wallace tree reduction architecture and 1.5 V full-swing BiCMOS dynamic logic circuit
|
Kuo, J.B.; Su, K.W.; Lou, J.H. |
臺大學術典藏 |
1994-06 |
A BiCMOS dynamic multiplier using Wallace tree reduction architecture and 1.5 V full-swing BiCMOS dynamic logic circuit
|
Kuo, J.B.; Su, K.W.; Lou, J.H.; Kuo, J.B.; Su, K.W.; Lou, J.H.; KuoJB |
國立臺灣大學 |
1994-05 |
Device-level analysis of a BiPMOS pull-down device structure for low-voltage dynamic BiCMOS VLSI
|
Kuo, J.B.; Su, K.W.; Lou, J.H.; Ma, Y.; Chen, S.S.; Chiang, C.S. |
臺大學術典藏 |
1994-05 |
Device-level analysis of a BiPMOS pull-down device structure for low-voltage dynamic BiCMOS VLSI
|
Kuo, J.B.; Su, K.W.; Lou, J.H.; Ma, Y.; Chen, S.S.; Chiang, C.S.; Kuo, J.B.; Su, K.W.; Lou, J.H.; Ma, Y.; Chen, S.S.; Chiang, C.S.; KuoJB |
國立臺灣大學 |
1994-02 |
Closed-form physical model for VLSI bipolar devices considering energy transport
|
Kuo, J.B.; Huang, H.J.; Lu, T.C. |
臺大學術典藏 |
1994-02 |
Closed-form physical model for VLSI bipolar devices considering energy transport
|
Kuo, J.B.; Huang, H.J.; Lu, T.C.; Kuo, J.B.; Huang, H.J.; Lu, T.C.; KuoJB |
國立臺灣大學 |
1994-01 |
Low-voltage BiCMOS dynamic minimum circuit using a parallel comparison algorithm for fuzzy controllers
|
Kuo, J.B.; Wang, J.Y.; Chen, Y.G. |
臺大學術典藏 |
1994-01 |
Low-voltage BiCMOS dynamic minimum circuit using a parallel comparison algorithm for fuzzy controllers
|
Kuo, J.B.; Wang, J.Y.; Chen, Y.G.; Kuo, J.B.; Wang, J.Y.; Chen, Y.G.; KuoJB |
國立臺灣大學 |
1993-11 |
1.5V BiCMOS dynamic multiplier using Wallace tree reduction architecture
|
Kuo, J.B.; Su, K.W.; Lou, J.H. |
國立臺灣大學 |
1993-11 |
Amorphous silicon TFT capacitance model using an effective temperature approach
|
Kuo, J.B.; Chen, S.S. |
臺大學術典藏 |
1993-11 |
1.5V BiCMOS dynamic multiplier using Wallace tree reduction architecture
|
KuoJB; Su, K.W.; Lou, J.H.; Kuo, J.B.; Kuo, J.B.; Su, K.W.; Lou, J.H. |
臺大學術典藏 |
1993-11 |
Amorphous silicon TFT capacitance model using an effective temperature approach
|
Kuo, J.B.; Chen, S.S.; Kuo, J.B.; Chen, S.S.; KuoJB |
國立臺灣大學 |
1993-10 |
Saturation region model for a-Si:H TFTs using a quasi-two-dimensional approach
|
Kuo, J.B.; Chen, S.S. |
國立臺灣大學 |
1993-10 |
An analytical back gate bias dependent threshold voltage model for SiGe-channel ultra-thin SOI PMOS devices
|
Kuo, J.B.; Tang, M.C.; Sim, J.H. |
臺大學術典藏 |
1993-10 |
Saturation region model for a-Si:H TFTs using a quasi-two-dimensional approach
|
Kuo, J.B.; Chen, S.S.; Kuo, J.B.; Chen, S.S.; KuoJB |
臺大學術典藏 |
1993-10 |
An analytical back gate bias dependent threshold voltage model for SiGe-channel ultra-thin SOI PMOS devices
|
Kuo, J.B.; Tang, M.C.; Sim, J.H.; Kuo, J.B.; Tang, M.C.; Sim, J.H.; KuoJB |
國立臺灣大學 |
1993-08 |
Analytical drain current model for a-Si:H TFTs by simultaneously considering localised deep and tail states
|
Kuo, J.B.; Chen, C.S. |
臺大學術典藏 |
1993-08 |
Analytical drain current model for a-Si:H TFTs by simultaneously considering localised deep and tail states
|
Kuo, J.B.; Chen, C.S.; Kuo, J.B.; Chen, C.S.; KuoJB |
國立臺灣大學 |
1993-05 |
A BiCMOS dynamic divider circuit using a nonrestoring iterative architecture with carry look ahead for CPU VLSI
|
Kuo, J.B.; Chen, H.P.; Huang, H.J. |
國立臺灣大學 |
1993-05 |
Accumulation-type vs. inversion-type of an ultra-thin SIO PMOS device operating at 300 K and 77 K: subthreshold behavior and pull-up switching performance of a CMOS inverter
|
Kuo, J.B.; Sim, J.H. |
國立臺灣大學 |
1993-05 |
A coded block neural network system suitable for VLSI implementation using an adaptive learning-rate epoch-based back propagation technique
|
Mao, M.W.; Chen, B.Y.; Kuo, J.B. |
臺大學術典藏 |
1993-05 |
A BiCMOS dynamic divider circuit using a nonrestoring iterative architecture with carry look ahead for CPU VLSI
|
Kuo, J.B.; Chen, H.P.; Huang, H.J.; Kuo, J.B.; Chen, H.P.; Huang, H.J.; KuoJB |
臺大學術典藏 |
1993-05 |
Accumulation-type vs. inversion-type of an ultra-thin SIO PMOS device operating at 300 K and 77 K: subthreshold behavior and pull-up switching performance of a CMOS inverter
|
Kuo, J.B.; Sim, J.H.; Kuo, J.B.; Sim, J.H.; KuoJB |
國立臺灣大學 |
1993-03 |
BiCMOS dynamic minimum circuit using a parallel comparison algorithm for fuzzy controllers
|
Chen, S.S.; Chiang, C.S.; Su, K.W.; Kuo, J.B. |
國立臺灣大學 |
1993 |
An Improved Analytical Short-Channel MOSFET Model Valid in All Regions of Operation for Analog/Digital Circuit Si[20642:0:4] 50300022:31:An Improved Analytical Short-Channel MOSFET Model Valid in All Regions of Operation for Analog/Digit
|
Chow, H. C.; 馮武雄; Kuo, J. B.; Chow, H. C.; Feng, Wu-Shiung; Kuo, J. B. |
國立臺灣大學 |
1992-10 |
Coded block neural network VLSI system using an adaptive learning-rate technique to train Chinese character patterns
|
Chen, B.Y.; Mao, M.W.; Kuo, J.B. |
國立臺灣大學 |
1992-10 |
A BiCMOS dynamic full adder circuit for VLSI implementation of high-speed parallel multipliers using Wallace tree reduction architecture
|
Kuo, J.B.; Liao, H.J.; Chen, H.P. |
Showing items 51-100 of 128 (3 Page(s) Totally) << < 1 2 3 > >> View [10|25|50] records per page
|