English  |  正體中文  |  简体中文  |  2822924  
???header.visitor??? :  30046538    ???header.onlineuser??? :  1136
???header.sponsordeclaration???
 
臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)
???ui.leftmenu.abouttair???

???ui.leftmenu.bartitle???

???index.news???

???ui.leftmenu.copyrighttitle???

???ui.leftmenu.link???

"kuo j b"???jsp.browse.items-by-author.description???

???jsp.browse.items-by-author.back???
???jsp.browse.items-by-author.order1??? ???jsp.browse.items-by-author.order2???

Showing items 61-85 of 128  (6 Page(s) Totally)
<< < 1 2 3 4 5 6 > >>
View [10|25|50] records per page

Institution Date Title Author
國立臺灣大學 1996-09 Analytical current conduction model for accumulation-mode SOI PMOS devices Su, K.W.; Kuo, J.B.
國立臺灣大學 1996 A velocity-overshoot capacitance model for 0.1 μm MOS transistors Kuo, J. B.; Chang, Y. W.; Lai, C. S.
國立臺灣大學 1995-10 SiC vs. Si: two-dimensional analysis of quasi-saturation behavior of DMOS devices operating at elevated temperatures Chang, Y.W.; Kuo, J.B.
國立臺灣大學 1995-10 An analytical delayed-turn-off model for 6H-SiC buried-channel NMOS devices considering incomplete ionization Su, K.W.; Kuo, J.B.
國立臺灣大學 1995-10 Accumulation-type vs. inversion-type: narrow channel effect in VLSI mesa-isolated fully-depleted ultra-thin SOI PMOS devices Su, K.W.; Kuo, J.B.
國立臺灣大學 1995-09 A high-speed 1.5 V clocked BiCMOS latch for BiCMOS dynamic pipelined digital logic VLSI systems Kuo, J.B.; Lou, J.H.; Su, K.W.
臺大學術典藏 1995-09 A high-speed 1.5 V clocked BiCMOS latch for BiCMOS dynamic pipelined digital logic VLSI systems Kuo, J.B.; Lou, J.H.; Su, K.W.; Kuo, J.B.; Lou, J.H.; Su, K.W.; KuoJB
國立臺灣大學 1995-05 A closed-form physical back-gate-bias dependent quasi-saturation model for SOI lateral DMOS devices with self-heating for circuit simulation Liu, C.M.; Shone, F.C.; Kuo, J.B.
國立臺灣大學 1994-12 A 1.5 V 10 MHz BiCMOS quasi-digital vector modulator for wireless communication IC Su, K.W.; Chen, Y.G.; Lai, C.S.; Kuo, J.B.; Wu, J.S.; Tso, H.W.
國立臺灣大學 1994-10 Back gate bias dependent quasi-saturation in a high-voltage SOI MOSFET: 2D analysis and closed-form analytical model Liu, C.M.; Kuo, J.B.
國立臺灣大學 1994-08 A 1.5 V BiCMOS dynamic subtracter circuit for low-voltage BiCMOS CPU VLSI Chen, Y.G.; Kuo, J.B.
國立臺灣大學 1994-07 A radical-partitioned neural network system using a modified Sigmoid function and a weight-dotted radical selector for large-volume Chinese characters recognition VLSI Kuo, J.B.; Chen, B.Y.; Mao, M.W.
臺大學術典藏 1994-07 A radical-partitioned neural network system using a modified Sigmoid function and a weight-dotted radical selector for large-volume Chinese characters recognition VLSI Kuo, J.B.; Chen, B.Y.; Mao, M.W.; Kuo, J.B.; Chen, B.Y.; Mao, M.W.; KuoJB
國立臺灣大學 1994-06 A BiCMOS dynamic multiplier using Wallace tree reduction architecture and 1.5 V full-swing BiCMOS dynamic logic circuit Kuo, J.B.; Su, K.W.; Lou, J.H.
臺大學術典藏 1994-06 A BiCMOS dynamic multiplier using Wallace tree reduction architecture and 1.5 V full-swing BiCMOS dynamic logic circuit Kuo, J.B.; Su, K.W.; Lou, J.H.; Kuo, J.B.; Su, K.W.; Lou, J.H.; KuoJB
國立臺灣大學 1994-05 Device-level analysis of a BiPMOS pull-down device structure for low-voltage dynamic BiCMOS VLSI Kuo, J.B.; Su, K.W.; Lou, J.H.; Ma, Y.; Chen, S.S.; Chiang, C.S.
臺大學術典藏 1994-05 Device-level analysis of a BiPMOS pull-down device structure for low-voltage dynamic BiCMOS VLSI Kuo, J.B.; Su, K.W.; Lou, J.H.; Ma, Y.; Chen, S.S.; Chiang, C.S.; Kuo, J.B.; Su, K.W.; Lou, J.H.; Ma, Y.; Chen, S.S.; Chiang, C.S.; KuoJB
國立臺灣大學 1994-02 Closed-form physical model for VLSI bipolar devices considering energy transport Kuo, J.B.; Huang, H.J.; Lu, T.C.
臺大學術典藏 1994-02 Closed-form physical model for VLSI bipolar devices considering energy transport Kuo, J.B.; Huang, H.J.; Lu, T.C.; Kuo, J.B.; Huang, H.J.; Lu, T.C.; KuoJB
國立臺灣大學 1994-01 Low-voltage BiCMOS dynamic minimum circuit using a parallel comparison algorithm for fuzzy controllers Kuo, J.B.; Wang, J.Y.; Chen, Y.G.
臺大學術典藏 1994-01 Low-voltage BiCMOS dynamic minimum circuit using a parallel comparison algorithm for fuzzy controllers Kuo, J.B.; Wang, J.Y.; Chen, Y.G.; Kuo, J.B.; Wang, J.Y.; Chen, Y.G.; KuoJB
國立臺灣大學 1993-11 1.5V BiCMOS dynamic multiplier using Wallace tree reduction architecture Kuo, J.B.; Su, K.W.; Lou, J.H.
國立臺灣大學 1993-11 Amorphous silicon TFT capacitance model using an effective temperature approach Kuo, J.B.; Chen, S.S.
臺大學術典藏 1993-11 1.5V BiCMOS dynamic multiplier using Wallace tree reduction architecture KuoJB; Su, K.W.; Lou, J.H.; Kuo, J.B.; Kuo, J.B.; Su, K.W.; Lou, J.H.
臺大學術典藏 1993-11 Amorphous silicon TFT capacitance model using an effective temperature approach Kuo, J.B.; Chen, S.S.; Kuo, J.B.; Chen, S.S.; KuoJB

Showing items 61-85 of 128  (6 Page(s) Totally)
<< < 1 2 3 4 5 6 > >>
View [10|25|50] records per page