臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)

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	2019臺灣學術機構典藏研討會
	機構典藏系統RC7版本已發佈

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Showing items 71-95 of 128 (6 Page(s) Totally)
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Institution	Date	Title	Author
國立臺灣大學	1994-08	A 1.5 V BiCMOS dynamic subtracter circuit for low-voltage BiCMOS CPU VLSI	Chen, Y.G.; Kuo, J.B.
國立臺灣大學	1994-07	A radical-partitioned neural network system using a modified Sigmoid function and a weight-dotted radical selector for large-volume Chinese characters recognition VLSI	Kuo, J.B.; Chen, B.Y.; Mao, M.W.
臺大學術典藏	1994-07	A radical-partitioned neural network system using a modified Sigmoid function and a weight-dotted radical selector for large-volume Chinese characters recognition VLSI	Kuo, J.B.; Chen, B.Y.; Mao, M.W.; Kuo, J.B.; Chen, B.Y.; Mao, M.W.; KuoJB
國立臺灣大學	1994-06	A BiCMOS dynamic multiplier using Wallace tree reduction architecture and 1.5 V full-swing BiCMOS dynamic logic circuit	Kuo, J.B.; Su, K.W.; Lou, J.H.
臺大學術典藏	1994-06	A BiCMOS dynamic multiplier using Wallace tree reduction architecture and 1.5 V full-swing BiCMOS dynamic logic circuit	Kuo, J.B.; Su, K.W.; Lou, J.H.; Kuo, J.B.; Su, K.W.; Lou, J.H.; KuoJB
國立臺灣大學	1994-05	Device-level analysis of a BiPMOS pull-down device structure for low-voltage dynamic BiCMOS VLSI	Kuo, J.B.; Su, K.W.; Lou, J.H.; Ma, Y.; Chen, S.S.; Chiang, C.S.
臺大學術典藏	1994-05	Device-level analysis of a BiPMOS pull-down device structure for low-voltage dynamic BiCMOS VLSI	Kuo, J.B.; Su, K.W.; Lou, J.H.; Ma, Y.; Chen, S.S.; Chiang, C.S.; Kuo, J.B.; Su, K.W.; Lou, J.H.; Ma, Y.; Chen, S.S.; Chiang, C.S.; KuoJB
國立臺灣大學	1994-02	Closed-form physical model for VLSI bipolar devices considering energy transport	Kuo, J.B.; Huang, H.J.; Lu, T.C.
臺大學術典藏	1994-02	Closed-form physical model for VLSI bipolar devices considering energy transport	Kuo, J.B.; Huang, H.J.; Lu, T.C.; Kuo, J.B.; Huang, H.J.; Lu, T.C.; KuoJB
國立臺灣大學	1994-01	Low-voltage BiCMOS dynamic minimum circuit using a parallel comparison algorithm for fuzzy controllers	Kuo, J.B.; Wang, J.Y.; Chen, Y.G.
臺大學術典藏	1994-01	Low-voltage BiCMOS dynamic minimum circuit using a parallel comparison algorithm for fuzzy controllers	Kuo, J.B.; Wang, J.Y.; Chen, Y.G.; Kuo, J.B.; Wang, J.Y.; Chen, Y.G.; KuoJB
國立臺灣大學	1993-11	1.5V BiCMOS dynamic multiplier using Wallace tree reduction architecture	Kuo, J.B.; Su, K.W.; Lou, J.H.
國立臺灣大學	1993-11	Amorphous silicon TFT capacitance model using an effective temperature approach	Kuo, J.B.; Chen, S.S.
臺大學術典藏	1993-11	1.5V BiCMOS dynamic multiplier using Wallace tree reduction architecture	KuoJB; Su, K.W.; Lou, J.H.; Kuo, J.B.; Kuo, J.B.; Su, K.W.; Lou, J.H.
臺大學術典藏	1993-11	Amorphous silicon TFT capacitance model using an effective temperature approach	Kuo, J.B.; Chen, S.S.; Kuo, J.B.; Chen, S.S.; KuoJB
國立臺灣大學	1993-10	Saturation region model for a-Si:H TFTs using a quasi-two-dimensional approach	Kuo, J.B.; Chen, S.S.
國立臺灣大學	1993-10	An analytical back gate bias dependent threshold voltage model for SiGe-channel ultra-thin SOI PMOS devices	Kuo, J.B.; Tang, M.C.; Sim, J.H.
臺大學術典藏	1993-10	Saturation region model for a-Si:H TFTs using a quasi-two-dimensional approach	Kuo, J.B.; Chen, S.S.; Kuo, J.B.; Chen, S.S.; KuoJB
臺大學術典藏	1993-10	An analytical back gate bias dependent threshold voltage model for SiGe-channel ultra-thin SOI PMOS devices	Kuo, J.B.; Tang, M.C.; Sim, J.H.; Kuo, J.B.; Tang, M.C.; Sim, J.H.; KuoJB
國立臺灣大學	1993-08	Analytical drain current model for a-Si:H TFTs by simultaneously considering localised deep and tail states	Kuo, J.B.; Chen, C.S.
臺大學術典藏	1993-08	Analytical drain current model for a-Si:H TFTs by simultaneously considering localised deep and tail states	Kuo, J.B.; Chen, C.S.; Kuo, J.B.; Chen, C.S.; KuoJB
國立臺灣大學	1993-05	A BiCMOS dynamic divider circuit using a nonrestoring iterative architecture with carry look ahead for CPU VLSI	Kuo, J.B.; Chen, H.P.; Huang, H.J.
國立臺灣大學	1993-05	Accumulation-type vs. inversion-type of an ultra-thin SIO PMOS device operating at 300 K and 77 K: subthreshold behavior and pull-up switching performance of a CMOS inverter	Kuo, J.B.; Sim, J.H.
國立臺灣大學	1993-05	A coded block neural network system suitable for VLSI implementation using an adaptive learning-rate epoch-based back propagation technique	Mao, M.W.; Chen, B.Y.; Kuo, J.B.
臺大學術典藏	1993-05	A BiCMOS dynamic divider circuit using a nonrestoring iterative architecture with carry look ahead for CPU VLSI	Kuo, J.B.; Chen, H.P.; Huang, H.J.; Kuo, J.B.; Chen, H.P.; Huang, H.J.; KuoJB

Showing items 71-95 of 128 (6 Page(s) Totally)
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