臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)

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	2019臺灣學術機構典藏研討會
	機構典藏系統RC7版本已發佈

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Institution	Date	Title	Author
臺大學術典藏	1993-05	Accumulation-type vs. inversion-type of an ultra-thin SIO PMOS device operating at 300 K and 77 K: subthreshold behavior and pull-up switching performance of a CMOS inverter	Kuo, J.B.; Sim, J.H.; Kuo, J.B.; Sim, J.H.; KuoJB
國立臺灣大學	1993-03	BiCMOS dynamic minimum circuit using a parallel comparison algorithm for fuzzy controllers	Chen, S.S.; Chiang, C.S.; Su, K.W.; Kuo, J.B.
國立臺灣大學	1993	An Improved Analytical Short-Channel MOSFET Model Valid in All Regions of Operation for Analog/Digital Circuit Si[20642:0:4] 50300022:31:An Improved Analytical Short-Channel MOSFET Model Valid in All Regions of Operation for Analog/Digit	Chow, H. C.; 馮武雄; Kuo, J. B.; Chow, H. C.; Feng, Wu-Shiung; Kuo, J. B.
國立臺灣大學	1992-10	Coded block neural network VLSI system using an adaptive learning-rate technique to train Chinese character patterns	Chen, B.Y.; Mao, M.W.; Kuo, J.B.
國立臺灣大學	1992-10	A BiCMOS dynamic full adder circuit for VLSI implementation of high-speed parallel multipliers using Wallace tree reduction architecture	Kuo, J.B.; Liao, H.J.; Chen, H.P.
國立臺灣大學	1992-10	Delayed-turn-on phenomenon in accumulation-type SOI pMOS device operating at liquid nitrogen temperature	Kuo, J.B.; Sim, J.H.
臺大學術典藏	1992-10	A BiCMOS dynamic full adder circuit for VLSI implementation of high-speed parallel multipliers using Wallace tree reduction architecture	Kuo, J.B.; Liao, H.J.; Chen, H.P.; Kuo, J.B.; Liao, H.J.; Chen, H.P.; KuoJB
臺大學術典藏	1992-10	Delayed-turn-on phenomenon in accumulation-type SOI pMOS device operating at liquid nitrogen temperature	Kuo, J.B.; Sim, J.H.; Kuo, J.B.; Sim, J.H.; KuoJB
國立臺灣大學	1992-07	Simple analytical model for short-channel MOS devices	Chow, H.-C.; Feng, W.-S.; Kuo, J.B.
國立臺灣大學	1992-06	BiCMOS dynamic full adder circuit for high-speed parallel multipliers	Chen, H.P.; Liao, H.J.; Kuo, J.B.
國立臺灣大學	1992-06	A radical-partitioned coded block adaptive neural network structure for large-volume Chinese characters recognition	Kuo, J.B.; Mao, M.W.
臺大學術典藏	1992-06	A radical-partitioned coded block adaptive neural network structure for large-volume Chinese characters recognition	Kuo, J.B.; Mao, M.W.; Kuo, J.B.; Mao, M.W.; KuoJB
國立臺灣大學	1992-02	BiCMOS dynamic Manchester carry look ahead circuit for high speed arithmetic unit VLSI	Kuo, J.B.; Liao, H.J.; Chen, H.P.
臺大學術典藏	1992-02	BiCMOS dynamic Manchester carry look ahead circuit for high speed arithmetic unit VLSI	Kuo, J.B.; Liao, H.J.; Chen, H.P.; KuoJB; Kuo, J.B.; Liao, H.J.; Chen, H.P.
國立臺灣大學	1991-12	Analogue adaptive neural network circuit	Chiang, M.L.; Lu, T.C.; Kuo, J.B.
國立臺灣大學	1991-09	A BiCMOS tristate buffer for high-speed microprocessor VLSI	Kuo, J.B.; Liao, H.J.
國立臺灣大學	1991-09	Device-level transient analysis of a 1 μm six-transistor BiCMOS inverter circuit using a large-scale quasi-3D device simulator	Kuo, J.B.; Chen, Y.W.
臺大學術典藏	1991-09	A BiCMOS tristate buffer for high-speed microprocessor VLSI	Kuo, J.B.; Liao, H.J.; Kuo, J.B.; Liao, H.J.; KuoJB
臺大學術典藏	1991-09	Device-level transient analysis of a 1 μm six-transistor BiCMOS inverter circuit using a large-scale quasi-3D device simulator	Kuo, J.B.; Chen, Y.W.Kuojb; Kuo, J.B.; Chen, Y.W.; KuoJB
國立臺灣大學	1991-07	BiCMOS edge detector with correlated-double-sampling readout circuit for pattern recognition neural network	Kuo, J.B.; Chou, T.L.; Wong, E.J.
臺大學術典藏	1991-07	BiCMOS edge detector with correlated-double-sampling readout circuit for pattern recognition neural network	Kuo, J.B.; Chou, T.L.; Wong, E.J.; Kuo, J.B.; Chou, T.L.; Wong, E.J.; KuoJB
國立臺灣大學	1991-06	A structured adaptive neural network for pattern recognition VLSI	Kuo, J.B.; Wong, E.J.; Chen, C.C.; Hsiao, C.C.
國立臺灣大學	1991-06	Scaling consideration of BiCMOS SRAMs	Tsaur, J.J.; Jih, C.W.; Tsaur, H.W.; Kuo, J.B.
國立臺灣大學	1991-06	A BiCMOS image sensor with a chopper-stabilized edge detector and a correlated-double-sampling readout circuit for pattern recognition neural network VLSI operating at 77 K	Chou, T.L.; Wong, E.J.; Kuo, J.B.
國立臺灣大學	1991-06	A one-transistor synapse circuit with an analog LMS adaptive feedback for neural network VLSI	Lu, T.C.; Chiang, M.L.; Kuo, J.B.

Showing items 96-120 of 128 (6 Page(s) Totally)
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