English  |  正體中文  |  简体中文  |  Total items :0  
Visitors :  52886165    Online Users :  889
Project Commissioned by the Ministry of Education
Project Executed by National Taiwan University Library
 
臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)
About TAIR

Browse By

News

Copyright

Related Links

"kuo po yi"

Return to Browse by Author
Sorting by Title Sort by Date

Showing items 16-25 of 41  (5 Page(s) Totally)
<< < 1 2 3 4 5 > >>
View [10|25|50] records per page

Institution Date Title Author
國立交通大學 2018-08-21T05:53:27Z Effects of Backchannel Passivation on Electrical Behavior of Hetero-Stacked a-IWO/IGZO Thin Film Transistors Liu, Po-Tsun; Chang, Chih-Hsiang; Kuo, Po-Yi; Chen, Po-Wen
國立交通大學 2018-08-21T05:53:19Z Mobility enhancement for high stability tungsten-doped indium-zinc oxide thin film transistors with a channel passivation layer Ruan, Dun-Bao; Liu, Po-Tsun; Chiu, Yu-Chuan; Kuo, Po-Yi; Yu, Min-Chin; Gan, Kai-Jhih; Chien, Ta-Chun; Sze, Simon M.
國立交通大學 2017-04-21T06:56:35Z High-performance sidewall damascened tri-gate poly-si TFTs with the strain proximity free technique and stress memorization technique Hsieh, Dong-Ru; Kuo, Po-Yi; Lin, Jer-Yi; Chen, Yi-Hsuan; Chang, Tien-Shun; Chao, Tien-Sheng
國立交通大學 2017-04-21T06:56:21Z Junctionless Poly-Si Nanowire Transistors With Low-Temperature Trimming Process for Monolithic 3-D IC Application Lin, Jer-Yi; Kuo, Po-Yi; Lin, Ko-Li; Chin, Chun-Chieh; Chao, Tien-Sheng
國立交通大學 2017-04-21T06:55:58Z High-Performance Pi-Gate Poly-Si Junctionless and Inversion Mode FET Hsieh, Dong-Ru; Lin, Jer-Yi; Kuo, Po-Yi; Chao, Tien-Sheng
國立交通大學 2017-04-21T06:48:46Z Fabrication and Characterization of Pi-Gate Poly-Si Junctionless and Inversion Mode Fin-FETs for 3-D IC Applications Hsieh, Don-Ru; Lin, Jer-Yi; Kuo, Po-Yi; Chao, Tien-Sheng
國立交通大學 2017-04-21T06:48:18Z Implantation Free GAA Double Spacer Poly-Si Nanowires Channel Junctionless FETs with Sub-1V Gate Operation and Near Ideal Subthreshold Swing Kuo, Po-Yi; Lin, Jer-Yi; Chao, Tien-Sheng
國立交通大學 2015-07-21T11:20:46Z High-Performance GAA Sidewall-Damascened Sub-10-nm In Situ n(+)-Doped Poly-Si NWs Channels Junctionless FETs Kuo, Po-Yi; Lu, Yi-Hsien; Chao, Tien-Sheng
國立交通大學 2014-12-16T06:14:01Z Manufacturing method of a semiconductor component with a nanowire channel Kuo Po-Yi; Chao Tien-Sheng; Lu Yi-Hsien
國立交通大學 2014-12-08T15:48:37Z Characteristics of SONOS-Type Flash Memory With In Situ Embedded Silicon Nanocrystals Chiang, Tsung-Yu; Wu, Yi-Hong; Ma, William Cheng-Yu; Kuo, Po-Yi; Wang, Kuan-Ti; Liao, Chia-Chun; Yeh, Chi-Ruei; Yang, Wen-Luh; Chao, Tien-Sheng

Showing items 16-25 of 41  (5 Page(s) Totally)
<< < 1 2 3 4 5 > >>
View [10|25|50] records per page