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Showing items 226-275 of 284 (6 Page(s) Totally)
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Institution	Date	Title	Author
國立臺灣大學	1993-06	YOR:a Yield Optimizing Routing Algorithm by Minimizing Critical Areas and Vias	郭斯彥; Kuo, Sy-Yen
國立臺灣大學	1993-06	Artificial Neural Networks for the Bipartite and K-Partite Subgraph Problems	Lai, J. S.; Ko, Y. J.; 郭斯彥; Lai, J. S.; Ko, Y. J.; Kuo, Sy-Yen
國立臺灣大學	1993-06	The Sea-of-Wires Array Synthesis System	Chen, I. Y.; Chen, G. L.; Hill, F. J.; 郭斯彥; Chen, I. Y.; Chen, G. L.; Hill, F. J.; Kuo, Sy-Yen
臺大學術典藏	1993-06	Artificial Neural Networks for the Bipartite and K-Partite Subgraph Problems	Lai, J. S.; Ko, Y. J.; Kuo, Sy-Yen; Lai, J. S.; Ko, Y. J.; 郭斯彥; Ko, Y. J.; Kuo, Sy-Yen
臺大學術典藏	1993-06	The Sea-of-Wires Array Synthesis System	Chen, G. L.; Hill, F. J.; Chen, I. Y.; Kuo, Sy-Yen; Chen, I. Y.; Chen, G. L.; Hill, F. J.; 郭斯彥; Chen, I. Y.; Hill, F. J.; Kuo, Sy-Yen
國立臺灣大學	1993-05	Concurrent Error Detection and Correction in Real Time Systolic Sorting Arrays	郭斯彥; Liang, S. C.; Kuo, Sy-Yen; Liang, S. C.
國立臺灣大學	1993	多晶片模組設計自動化與測試系統總計劃(I)	林呈祥; 郭斯彥; Lin, Chen-Shang; Kuo, Sy-Yen
國立臺灣大學	1993	多晶片模組可測性設計與偵錯	郭斯彥; Kuo, Sy-Yen
國立臺灣大學	1992-12	Efficient Backtracking Decision Heuristics and Evaluation for Test Generation	郭斯彥; Kuo, Sy-Yen
國立臺灣大學	1992-10	Efficient Reconfiguration Algorithms for Degradable VLSI/WSI Arrays	郭斯彥; Chen, I. Y.; Kuo, Sy-Yen; Chen, I. Y.
國立臺灣大學	1992-10	Modeling and Algorithms for Spare Allocation in Reconfigurable VLSI	郭斯彥; Fuchs, W. K.; Kuo, Sy-Yen; Fuchs, W. K.
國立臺灣大學	1992-09	Locating logic design errors via test generation and don't-care propagation	Kuo, Sy-Yen
臺大學術典藏	1992-09	Locating logic design errors via test generation and don't-care propagation	Kuo, Sy-Yen; Kuo, Sy-Yen
國立臺灣大學	1992-07	Fault Diagnosis and Spare Allocation for Yield Enhancement in Large Reconfigurable PLAs	郭斯彥; Fuchs, S. Y.; Kuo, Sy-Yen; Fuchs, S. Y.
國立臺灣大學	1992-03	YOR: a yield optimizing routing algorithm by minimizing critical area and vias	Kuo, Sy-Yen
國立臺灣大學	1992-03	Testable Design of Systolic Arrays for Discrete Cosine Transform	Lu, S. K.; Wu, C. W.; 郭斯彥; Lu, S. K.; Wu, C. W.; Kuo, Sy-Yen
國立臺灣大學	1992-03	YOR:a Yield Optimizing Routing Algorithm by Minimizing Critical Areas and Vias	郭斯彥; Kuo, Sy-Yen
臺大學術典藏	1992-03	Testable Design of Systolic Arrays for Discrete Cosine Transform	Wu, C. W.; Lu, S. K.; Kuo, Sy-Yen; Lu, S. K.; Wu, C. W.; 郭斯彥; Lu, S. K.; Kuo, Sy-Yen
臺大學術典藏	1992-03	YOR: a yield optimizing routing algorithm by minimizing critical area and vias	Kuo, Sy-Yen; Kuo, Sy-Yen
國立臺灣大學	1992-02	Defect-Tolerant Hierarchical Sorting Networks for Wafer-Scale Integration	郭斯彥; Liang, S. C.; Kuo, Sy-Yen; Liang, S. C.
國立臺灣大學	1992-01	Design and analysis of defect tolerant hierarchical sorting networks	Kuo, Sy-Yen; Liang, Sheng-Chiech
臺大學術典藏	1992-01	Design and analysis of defect tolerant hierarchical sorting networks	Kuo, Sy-Yen; Liang, Sheng-Chiech; Kuo, Sy-Yen; Liang, Sheng-Chiech
國立臺灣大學	1992	Design of Easily Testable VLSI Arrays for Discrete Cosine Transform	Lu, S. K.; Wu, C. W.; 郭斯彥; Lu, S. K.; Wu, C. W.; Kuo, Sy-Yen
國立臺灣大學	1992	Optimal Group Diagnosis Procedures for VLSI/WSI Array Architectures	王弓; 郭斯彥; Wang, Kung; Kuo, Sy-Yen
臺大學術典藏	1992	Design of Easily Testable VLSI Arrays for Discrete Cosine Transform	Lu, S. K.; Wu, C. W.; Kuo, Sy-Yen; Lu, S. K.; Wu, C. W.; 郭斯彥; Kuo, Sy-Yen
臺大學術典藏	1992	Optimal Group Diagnosis Procedures for VLSI/WSI Array Architectures	Wang, Kung; Kuo, Sy-Yen; Wang, Kung; Kuo, Sy-Yen
國立臺灣大學	1991-09	Fault Diagnosis in Reconfigurable VLSI and WSI Arrays	郭斯彥; 王弓; Kuo, Sy-Yen; Wang, Kung
國立臺灣大學	1991-08	Design and Evaluation of Fault-Tolerant Interleaved Memory Systems	郭斯彥; Louri, A.; Liang, S. C.; Lu, S. K.; Wu, C. W.; Kuo, Sy-Yen; Louri, A.; Liang, S. C.; Lu, S. K.; Wu, C. W.
臺大學術典藏	1991-08	Design and Evaluation of Fault-Tolerant Interleaved Memory Systems	Lu, S. K.; Wu, C. W.; Kuo, Sy-Yen; Liang, S. C.; 郭斯彥; Liang, S. C.; Louri, A.; Louri, A.; Liang, S. C.; Lu, S. K.; Wu, C. W.; Kuo, Sy-Yen
國立臺灣大學	1991-01	Reconfigurable Cube-Connected Cycles Architectures	郭斯彥; Fuchs, W. K.; Kuo, Sy-Yen; Fuchs, W. K.
國立臺灣大學	1991-01	VHDL-Based Design and Analysis of Defect Tolerant VLSI/WSI Array Architectures	郭斯彥; 王弓; Kuo, Sy-Yen; Wang, Kung
臺大學術典藏	1991-01	VHDL-Based Design and Analysis of Defect Tolerant VLSI/WSI Array Architectures	Kuo, Sy-Yen; Wang, Kung; Kuo, Sy-Yen; Wang, Kung
國立臺灣大學	1991	Efficient Parallel Sorting and Merging Algorithms for Two-Dimensional Mesh-Connected Processor Arrays	郭斯彥; Liang, S. C.; Kuo, Sy-Yen; Liang, S. C.
國立臺灣大學	1991	Efficient Reconfiguration Algorithms for Degradable VLSI/WSI Arrays	郭斯彥; Chen, I. Y.; Kuo, Sy-Yen; Chen, I. Y.
臺大學術典藏	1991	Efficient Parallel Sorting and Merging Algorithms for Two-Dimensional Mesh-Connected Processor Arrays	Liang, S. C.; Kuo, Sy-Yen; 郭斯彥; Liang, S. C.; Kuo, Sy-Yen
臺大學術典藏	1991	Efficient Reconfiguration Algorithms for Degradable VLSI/WSI Arrays	Chen, I. Y.; Kuo, Sy-Yen; 郭斯彥; Chen, I. Y.; Kuo, Sy-Yen
國立臺灣大學	1990-06	Concurrent Error Detection and Correction in Real Time Systolic Sorting Arrays	Liang, S. C.; 郭斯彥; Liang, S. C.; Kuo, Sy-Yen
臺大學術典藏	1990-06	Concurrent Error Detection and Correction in Real Time Systolic Sorting Arrays	Liang, S. C.; Kuo, Sy-Yen; Liang, S. C.; 郭斯彥; Kuo, Sy-Yen
國立臺灣大學	1990-05	Fault Tolerance Techniques for Systoilc Arrays	Abraham, J. A.; Banerjee, P.; Chen, C. Y.; Fuchs, W. K.; 郭斯彥; Reddy, A. L. N.; Abraham, J. A.; Banerjee, P.; Chen, C. Y.; Fuchs, W. K.; Kuo, Sy-Yen; Reddy, A. L. N.
國立臺灣大學	1990-04	Fault Tolerant VLSI Systolic Median Filters	Liang, S. C.; 郭斯彥; Liang, S. C.; Kuo, Sy-Yen
臺大學術典藏	1990-04	Fault Tolerant VLSI Systolic Median Filters	Liang, S. C.; Kuo, Sy-Yen; Liang, S. C.; 郭斯彥; Liang, S. C.; Kuo, Sy-Yen
國立臺灣大學	1990-01	Fault Tolerant WSI Sorting Networks	Liang, S. C.; 郭斯彥; Liang, S. C.; Kuo, Sy-Yen
臺大學術典藏	1990-01	Fault Tolerant WSI Sorting Networks	Liang, S. C.; Kuo, Sy-Yen; Liang, S. C.; 郭斯彥; Liang, S. C.; Kuo, Sy-Yen
國立臺灣大學	1989-11	A VLSI Design of Systolic Tree-Searched Vector Quantizer for EOS on Board SAR Processor	Fang, W. C.; Chang, C. Y.; 郭斯彥; Nixon, R. H.; Curlander, J. C.; Fang, W. C.; Chang, C. Y.; Kuo, Sy-Yen; Nixon, R. H.; Curlander, J. C.
臺大學術典藏	1989-11	A VLSI Design of Systolic Tree-Searched Vector Quantizer for EOS on Board SAR Processor	Fang, W. C.; Nixon, R. H.; Curlander, J. C.; Chang, C. Y.; Kuo, Sy-Yen; Fang, W. C.; Chang, C. Y.; 郭斯彥; Nixon, R. H.; Curlander, J. C.; Fang, W. C.; Chang, C. Y.; Kuo, Sy-Yen; Nixon, R. H.
國立臺灣大學	1989	Design and Analysis of Defect Tolerant Hierarchical Sorting Networks	郭斯彥; Liang, S. C.; Kuo, Sy-Yen; Liang, S. C.
國立臺灣大學	1989	Fault Diagnosis in VLSI/WSI Processor Arrays	郭斯彥; 王弓; Kuo, Sy-Yen; Wang, Kung
臺大學術典藏	1989	Fault Diagnosis in VLSI/WSI Processor Arrays	Kuo, Sy-Yen; Wang, Kung; Kuo, Sy-Yen; Wang, Kung
國立臺灣大學	1988-06	Spare Allocation and Reconfiguration in Large Area VLSI	郭斯彥; Fuchs, W. K.; Kuo, Sy-Yen; Fuchs, W. K.
臺大學術典藏	1988-06	Spare Allocation and Reconfiguration in Large Area VLSI	Fuchs, W. K.; Kuo, Sy-Yen; 郭斯彥; Fuchs, W. K.; Kuo, Sy-Yen

Showing items 226-275 of 284 (6 Page(s) Totally)
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