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Showing items 231-255 of 284 (12 Page(s) Totally)
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| 國立臺灣大學 |
1993-05 |
Concurrent Error Detection and Correction in Real Time Systolic Sorting Arrays
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郭斯彥; Liang, S. C.; Kuo, Sy-Yen; Liang, S. C. |
| 國立臺灣大學 |
1993 |
多晶片模組設計自動化與測試系統總計劃(I)
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林呈祥; 郭斯彥; Lin, Chen-Shang; Kuo, Sy-Yen |
| 國立臺灣大學 |
1993 |
多晶片模組可測性設計與偵錯
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郭斯彥; Kuo, Sy-Yen |
| 國立臺灣大學 |
1992-12 |
Efficient Backtracking Decision Heuristics and Evaluation for Test Generation
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郭斯彥; Kuo, Sy-Yen |
| 國立臺灣大學 |
1992-10 |
Efficient Reconfiguration Algorithms for Degradable VLSI/WSI Arrays
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郭斯彥; Chen, I. Y.; Kuo, Sy-Yen; Chen, I. Y. |
| 國立臺灣大學 |
1992-10 |
Modeling and Algorithms for Spare Allocation in Reconfigurable VLSI
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郭斯彥; Fuchs, W. K.; Kuo, Sy-Yen; Fuchs, W. K. |
| 國立臺灣大學 |
1992-09 |
Locating logic design errors via test generation and don't-care propagation
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Kuo, Sy-Yen |
| 臺大學術典藏 |
1992-09 |
Locating logic design errors via test generation and don't-care propagation
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Kuo, Sy-Yen; Kuo, Sy-Yen |
| 國立臺灣大學 |
1992-07 |
Fault Diagnosis and Spare Allocation for Yield Enhancement in Large Reconfigurable PLAs
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郭斯彥; Fuchs, S. Y.; Kuo, Sy-Yen; Fuchs, S. Y. |
| 國立臺灣大學 |
1992-03 |
YOR: a yield optimizing routing algorithm by minimizing critical area and vias
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Kuo, Sy-Yen |
| 國立臺灣大學 |
1992-03 |
Testable Design of Systolic Arrays for Discrete Cosine Transform
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Lu, S. K.; Wu, C. W.; 郭斯彥; Lu, S. K.; Wu, C. W.; Kuo, Sy-Yen |
| 國立臺灣大學 |
1992-03 |
YOR:a Yield Optimizing Routing Algorithm by Minimizing Critical Areas and Vias
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郭斯彥; Kuo, Sy-Yen |
| 臺大學術典藏 |
1992-03 |
Testable Design of Systolic Arrays for Discrete Cosine Transform
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Wu, C. W.; Lu, S. K.; Kuo, Sy-Yen; Lu, S. K.; Wu, C. W.; 郭斯彥; Lu, S. K.; Kuo, Sy-Yen |
| 臺大學術典藏 |
1992-03 |
YOR: a yield optimizing routing algorithm by minimizing critical area and vias
|
Kuo, Sy-Yen; Kuo, Sy-Yen |
| 國立臺灣大學 |
1992-02 |
Defect-Tolerant Hierarchical Sorting Networks for Wafer-Scale Integration
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郭斯彥; Liang, S. C.; Kuo, Sy-Yen; Liang, S. C. |
| 國立臺灣大學 |
1992-01 |
Design and analysis of defect tolerant hierarchical sorting networks
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Kuo, Sy-Yen; Liang, Sheng-Chiech |
| 臺大學術典藏 |
1992-01 |
Design and analysis of defect tolerant hierarchical sorting networks
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Kuo, Sy-Yen; Liang, Sheng-Chiech; Kuo, Sy-Yen; Liang, Sheng-Chiech |
| 國立臺灣大學 |
1992 |
Design of Easily Testable VLSI Arrays for Discrete Cosine Transform
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Lu, S. K.; Wu, C. W.; 郭斯彥; Lu, S. K.; Wu, C. W.; Kuo, Sy-Yen |
| 國立臺灣大學 |
1992 |
Optimal Group Diagnosis Procedures for VLSI/WSI Array Architectures
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王弓; 郭斯彥; Wang, Kung; Kuo, Sy-Yen |
| 臺大學術典藏 |
1992 |
Design of Easily Testable VLSI Arrays for Discrete Cosine Transform
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Lu, S. K.; Wu, C. W.; Kuo, Sy-Yen; Lu, S. K.; Wu, C. W.; 郭斯彥; Kuo, Sy-Yen |
| 臺大學術典藏 |
1992 |
Optimal Group Diagnosis Procedures for VLSI/WSI Array Architectures
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Wang, Kung; Kuo, Sy-Yen; Wang, Kung; Kuo, Sy-Yen |
| 國立臺灣大學 |
1991-09 |
Fault Diagnosis in Reconfigurable VLSI and WSI Arrays
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郭斯彥; 王弓; Kuo, Sy-Yen; Wang, Kung |
| 國立臺灣大學 |
1991-08 |
Design and Evaluation of Fault-Tolerant Interleaved Memory Systems
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郭斯彥; Louri, A.; Liang, S. C.; Lu, S. K.; Wu, C. W.; Kuo, Sy-Yen; Louri, A.; Liang, S. C.; Lu, S. K.; Wu, C. W. |
| 臺大學術典藏 |
1991-08 |
Design and Evaluation of Fault-Tolerant Interleaved Memory Systems
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Lu, S. K.; Wu, C. W.; Kuo, Sy-Yen; Liang, S. C.; 郭斯彥; Liang, S. C.; Louri, A.; Louri, A.; Liang, S. C.; Lu, S. K.; Wu, C. W.; Kuo, Sy-Yen |
| 國立臺灣大學 |
1991-01 |
Reconfigurable Cube-Connected Cycles Architectures
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郭斯彥; Fuchs, W. K.; Kuo, Sy-Yen; Fuchs, W. K. |
Showing items 231-255 of 284 (12 Page(s) Totally)
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