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Institution Date Title Author
臺大學術典藏 2004-07 Evolution of low-voltage CMOS digital VLSI circuits using bootstrap technique Kuo, J.B.Kuojb; Kuo, J.B.; KuoJB
臺大學術典藏 2003-11 Analysis of gate misalignment effect on the threshold voltage of double-gate (DG) ultrathin fully-depleted (FD) silicon-on-insulator (SOI) NMOS devices using a compact model considering fringing electric field effect Kuo, J.B.; Sun, E.C.; Lin, M.T.Kuojb; Kuo, J.B.; Sun, E.C.; Lin, M.T.; KuoJB
臺大學術典藏 2000-06 SPICE compact modeling of PD-SOI CMOS devices Kuo, J.B.; Kuo, J.B.; KuoJB
臺大學術典藏 1997-10 Compact current model for mesa-isolated fully-depleted ultrathin SOI NMOS devices considering sidewall-related narrow channel effects Kuo, J.B.; Su, K.W.; Kuo, J.B.; Su, K.W.; KuoJB
臺大學術典藏 1995-09 A high-speed 1.5 V clocked BiCMOS latch for BiCMOS dynamic pipelined digital logic VLSI systems Kuo, J.B.; Lou, J.H.; Su, K.W.; Kuo, J.B.; Lou, J.H.; Su, K.W.; KuoJB
臺大學術典藏 1994-07 A radical-partitioned neural network system using a modified Sigmoid function and a weight-dotted radical selector for large-volume Chinese characters recognition VLSI Kuo, J.B.; Chen, B.Y.; Mao, M.W.; Kuo, J.B.; Chen, B.Y.; Mao, M.W.; KuoJB
臺大學術典藏 1994-06 A BiCMOS dynamic multiplier using Wallace tree reduction architecture and 1.5 V full-swing BiCMOS dynamic logic circuit Kuo, J.B.; Su, K.W.; Lou, J.H.; Kuo, J.B.; Su, K.W.; Lou, J.H.; KuoJB
臺大學術典藏 1994-05 Device-level analysis of a BiPMOS pull-down device structure for low-voltage dynamic BiCMOS VLSI Kuo, J.B.; Su, K.W.; Lou, J.H.; Ma, Y.; Chen, S.S.; Chiang, C.S.; Kuo, J.B.; Su, K.W.; Lou, J.H.; Ma, Y.; Chen, S.S.; Chiang, C.S.; KuoJB
臺大學術典藏 1994-02 Closed-form physical model for VLSI bipolar devices considering energy transport Kuo, J.B.; Huang, H.J.; Lu, T.C.; Kuo, J.B.; Huang, H.J.; Lu, T.C.; KuoJB
臺大學術典藏 1994-01 Low-voltage BiCMOS dynamic minimum circuit using a parallel comparison algorithm for fuzzy controllers Kuo, J.B.; Wang, J.Y.; Chen, Y.G.; Kuo, J.B.; Wang, J.Y.; Chen, Y.G.; KuoJB

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