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"kuojb"的相关文件
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| 臺大學術典藏 |
1994-07 |
A radical-partitioned neural network system using a modified Sigmoid function and a weight-dotted radical selector for large-volume Chinese characters recognition VLSI
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Kuo, J.B.; Chen, B.Y.; Mao, M.W.; Kuo, J.B.; Chen, B.Y.; Mao, M.W.; KuoJB |
| 臺大學術典藏 |
1994-06 |
A BiCMOS dynamic multiplier using Wallace tree reduction architecture and 1.5 V full-swing BiCMOS dynamic logic circuit
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Kuo, J.B.; Su, K.W.; Lou, J.H.; Kuo, J.B.; Su, K.W.; Lou, J.H.; KuoJB |
| 臺大學術典藏 |
1994-05 |
Device-level analysis of a BiPMOS pull-down device structure for low-voltage dynamic BiCMOS VLSI
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Kuo, J.B.; Su, K.W.; Lou, J.H.; Ma, Y.; Chen, S.S.; Chiang, C.S.; Kuo, J.B.; Su, K.W.; Lou, J.H.; Ma, Y.; Chen, S.S.; Chiang, C.S.; KuoJB |
| 臺大學術典藏 |
1994-02 |
Closed-form physical model for VLSI bipolar devices considering energy transport
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Kuo, J.B.; Huang, H.J.; Lu, T.C.; Kuo, J.B.; Huang, H.J.; Lu, T.C.; KuoJB |
| 臺大學術典藏 |
1994-01 |
Low-voltage BiCMOS dynamic minimum circuit using a parallel comparison algorithm for fuzzy controllers
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Kuo, J.B.; Wang, J.Y.; Chen, Y.G.; Kuo, J.B.; Wang, J.Y.; Chen, Y.G.; KuoJB |
| 臺大學術典藏 |
1993-11 |
1.5V BiCMOS dynamic multiplier using Wallace tree reduction architecture
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KuoJB; Su, K.W.; Lou, J.H.; Kuo, J.B.; Kuo, J.B.; Su, K.W.; Lou, J.H. |
| 臺大學術典藏 |
1993-11 |
Amorphous silicon TFT capacitance model using an effective temperature approach
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Kuo, J.B.; Chen, S.S.; Kuo, J.B.; Chen, S.S.; KuoJB |
| 臺大學術典藏 |
1993-10 |
Saturation region model for a-Si:H TFTs using a quasi-two-dimensional approach
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Kuo, J.B.; Chen, S.S.; Kuo, J.B.; Chen, S.S.; KuoJB |
| 臺大學術典藏 |
1993-10 |
An analytical back gate bias dependent threshold voltage model for SiGe-channel ultra-thin SOI PMOS devices
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Kuo, J.B.; Tang, M.C.; Sim, J.H.; Kuo, J.B.; Tang, M.C.; Sim, J.H.; KuoJB |
| 臺大學術典藏 |
1993-08 |
Analytical drain current model for a-Si:H TFTs by simultaneously considering localised deep and tail states
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Kuo, J.B.; Chen, C.S.; Kuo, J.B.; Chen, C.S.; KuoJB |
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