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Taiwan Academic Institutional Repository >
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"kuojb"
Showing items 11-27 of 27 (1 Page(s) Totally)
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| 臺大學術典藏 |
1993-11 |
1.5V BiCMOS dynamic multiplier using Wallace tree reduction architecture
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KuoJB; Su, K.W.; Lou, J.H.; Kuo, J.B.; Kuo, J.B.; Su, K.W.; Lou, J.H. |
| 臺大學術典藏 |
1993-11 |
Amorphous silicon TFT capacitance model using an effective temperature approach
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Kuo, J.B.; Chen, S.S.; Kuo, J.B.; Chen, S.S.; KuoJB |
| 臺大學術典藏 |
1993-10 |
Saturation region model for a-Si:H TFTs using a quasi-two-dimensional approach
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Kuo, J.B.; Chen, S.S.; Kuo, J.B.; Chen, S.S.; KuoJB |
| 臺大學術典藏 |
1993-10 |
An analytical back gate bias dependent threshold voltage model for SiGe-channel ultra-thin SOI PMOS devices
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Kuo, J.B.; Tang, M.C.; Sim, J.H.; Kuo, J.B.; Tang, M.C.; Sim, J.H.; KuoJB |
| 臺大學術典藏 |
1993-08 |
Analytical drain current model for a-Si:H TFTs by simultaneously considering localised deep and tail states
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Kuo, J.B.; Chen, C.S.; Kuo, J.B.; Chen, C.S.; KuoJB |
| 臺大學術典藏 |
1993-05 |
A BiCMOS dynamic divider circuit using a nonrestoring iterative architecture with carry look ahead for CPU VLSI
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Kuo, J.B.; Chen, H.P.; Huang, H.J.; Kuo, J.B.; Chen, H.P.; Huang, H.J.; KuoJB |
| 臺大學術典藏 |
1993-05 |
Accumulation-type vs. inversion-type of an ultra-thin SIO PMOS device operating at 300 K and 77 K: subthreshold behavior and pull-up switching performance of a CMOS inverter
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Kuo, J.B.; Sim, J.H.; Kuo, J.B.; Sim, J.H.; KuoJB |
| 臺大學術典藏 |
1992-10 |
A BiCMOS dynamic full adder circuit for VLSI implementation of high-speed parallel multipliers using Wallace tree reduction architecture
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Kuo, J.B.; Liao, H.J.; Chen, H.P.; Kuo, J.B.; Liao, H.J.; Chen, H.P.; KuoJB |
| 臺大學術典藏 |
1992-10 |
Delayed-turn-on phenomenon in accumulation-type SOI pMOS device operating at liquid nitrogen temperature
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Kuo, J.B.; Sim, J.H.; Kuo, J.B.; Sim, J.H.; KuoJB |
| 臺大學術典藏 |
1992-06 |
A radical-partitioned coded block adaptive neural network structure for large-volume Chinese characters recognition
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Kuo, J.B.; Mao, M.W.; Kuo, J.B.; Mao, M.W.; KuoJB |
| 臺大學術典藏 |
1992-02 |
BiCMOS dynamic Manchester carry look ahead circuit for high speed arithmetic unit VLSI
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Kuo, J.B.; Liao, H.J.; Chen, H.P.; KuoJB; Kuo, J.B.; Liao, H.J.; Chen, H.P. |
| 臺大學術典藏 |
1991-09 |
A BiCMOS tristate buffer for high-speed microprocessor VLSI
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Kuo, J.B.; Liao, H.J.; Kuo, J.B.; Liao, H.J.; KuoJB |
| 臺大學術典藏 |
1991-09 |
Device-level transient analysis of a 1 μm six-transistor BiCMOS inverter circuit using a large-scale quasi-3D device simulator
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Kuo, J.B.; Chen, Y.W.Kuojb; Kuo, J.B.; Chen, Y.W.; KuoJB |
| 臺大學術典藏 |
1991-07 |
BiCMOS edge detector with correlated-double-sampling readout circuit for pattern recognition neural network
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Kuo, J.B.; Chou, T.L.; Wong, E.J.; Kuo, J.B.; Chou, T.L.; Wong, E.J.; KuoJB |
| 臺大學術典藏 |
1991-06 |
A structured adaptive neural network for pattern recognition VLSI
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Kuo, J.B.; Wong, E.J.; Chen, C.C.; Hsiao, C.C.; Kuo, J.B.; Wong, E.J.; Chen, C.C.; Hsiao, C.C.; KuoJB |
| 臺大學術典藏 |
1991-05 |
Device-level analysis of a 1 μm BiCMOS inverter circuit operating at 77 K using a modified PISCES program
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Kuo, J.B.; Chen, Y.W.; Lou, K.H.; Kuo, J.B.; Chen, Y.W.; Lou, K.H.; KuoJB |
| 臺大學術典藏 |
1991-05 |
A coded block adaptive neural network structure for pattern recognition VLSI
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Kuo, J.B.; Chen, Y.K.; Lu, Y.H.; Mao, W.C.; KuoJB; Kuo, J.B.; Chen, Y.K.; Lu, Y.H.; Mao, W.C |
Showing items 11-27 of 27 (1 Page(s) Totally)
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