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Showing items 21-27 of 27 (1 Page(s) Totally)
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| 臺大學術典藏 |
1992-02 |
BiCMOS dynamic Manchester carry look ahead circuit for high speed arithmetic unit VLSI
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Kuo, J.B.; Liao, H.J.; Chen, H.P.; KuoJB; Kuo, J.B.; Liao, H.J.; Chen, H.P. |
| 臺大學術典藏 |
1991-09 |
A BiCMOS tristate buffer for high-speed microprocessor VLSI
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Kuo, J.B.; Liao, H.J.; Kuo, J.B.; Liao, H.J.; KuoJB |
| 臺大學術典藏 |
1991-09 |
Device-level transient analysis of a 1 μm six-transistor BiCMOS inverter circuit using a large-scale quasi-3D device simulator
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Kuo, J.B.; Chen, Y.W.Kuojb; Kuo, J.B.; Chen, Y.W.; KuoJB |
| 臺大學術典藏 |
1991-07 |
BiCMOS edge detector with correlated-double-sampling readout circuit for pattern recognition neural network
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Kuo, J.B.; Chou, T.L.; Wong, E.J.; Kuo, J.B.; Chou, T.L.; Wong, E.J.; KuoJB |
| 臺大學術典藏 |
1991-06 |
A structured adaptive neural network for pattern recognition VLSI
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Kuo, J.B.; Wong, E.J.; Chen, C.C.; Hsiao, C.C.; Kuo, J.B.; Wong, E.J.; Chen, C.C.; Hsiao, C.C.; KuoJB |
| 臺大學術典藏 |
1991-05 |
Device-level analysis of a 1 μm BiCMOS inverter circuit operating at 77 K using a modified PISCES program
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Kuo, J.B.; Chen, Y.W.; Lou, K.H.; Kuo, J.B.; Chen, Y.W.; Lou, K.H.; KuoJB |
| 臺大學術典藏 |
1991-05 |
A coded block adaptive neural network structure for pattern recognition VLSI
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Kuo, J.B.; Chen, Y.K.; Lu, Y.H.; Mao, W.C.; KuoJB; Kuo, J.B.; Chen, Y.K.; Lu, Y.H.; Mao, W.C |
Showing items 21-27 of 27 (1 Page(s) Totally)
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