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Showing items 1-17 of 17  (1 Page(s) Totally)
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Institution Date Title Author
國立高雄大學 2008-10 Significant improvement of 45 nm and beyond complementary metal oxide semiconductor field effect transistor performance with fully silicided and ultimate spacer process technology Hsu, Chia-Wei; Fang, Yean-Kuen; Lin, Chien-Ting; Yeh, Wen-Kuan; Hsu, Che-Hua; Lai, Chieh-Ming; Cheng, Li-Wei; Ma, Mike
國立成功大學 2008-09-01 Significant improvement of 45 nm and beyond complementary metal oxide semiconductor field effect transistor performance with fully silicided and ultimate spacer process technology Hsu, Chia-Wei; Fang, Yean-Kuen; Lin, Chien-Ting; Yeh, Wen-Kuan; Hsu, Che-Hua; Lai, Chieh-Ming; Cheng, Li-Wei; Ma, Mike
國立高雄大學 2007-05 Impacts of notched-gate structure on contact etch stop layer (CESL) stressed 90-nm nMOSFET Lin, Chien-Ting; Fang, Yean-Kuen; Yeh, Wen-Kuan; Lai, Chieh-Ming; Hsu, Che-Hua; Cheng, Li-Wei; Ma, Guang-Hwa
國立成功大學 2007-05 Impacts of notched-gate structure on contact etch stop layer (CESL) stressed 90-nm nMOSFET Lin, Chien-Ting; Fang, Yean-Kuen; Yeh, Wen-Kuan; Lai, Chieh-Ming; Hsu, Che-Hua; Cheng, Li-Wei; Ma, Guang-Hwa
國立高雄大學 2007-04-30 Efficient mobility enhancement engineering on 65 nm fully silicide complementary metal-oxide-semiconductor field-effect-transistors using second contect etch stop layer process Lai, Chieh-Ming; Fang, Yean-Kuen; Lin, Chien-Ting; Yeh, Wen-Kuan
國立成功大學 2007-04 Efficient mobility enhancement engineering on 65 nm fully silicide complementary metal-oxide-semiconductor field-effect-transistors using second contect etch stop layer process Lai, Chieh-Ming; Fang, Yean-Kuen; Lin, Chien-Ting; Yeh, Wen-Kuan
國立成功大學 2007-04 Extra bonus on transistor optimization with stress enhanced notched-gate technology for sub-90 nm complementary metal oxide semiconductor field effect transistor Lin, Chien-Ting; Fang, Yean-Kuen; Lai, Chieh-Ming; Yeh, Wen-Kuan; Hsu, Che-Hua; Cheng, Li-Wei; Huang, Yao-Tsung; Ma, Guang Hwa
國立高雄大學 2007-02 A novel strain method for enhancement of 90-nm node and beyond FUSI-gated CMOS performance Lin, Chien-Ting; Fang, Yean-Kuen; Yeh, Wen-Kuan; Lee, Tung-Hsing; Chen, Ming-Shing; Lai, Chieh-Ming; Hsu, Che-Hua; Chen, Liang-Wei; Cheng, Li-Wei; Ma, Mike
國立高雄大學 2007-02 The investigation of post-annealing-induced defects behavior on 90-nm in halo nMOSFETs with low-frequency noise and charge-pumping measuring Lai, Chieh-Ming; Fang, Yean-Kuen; Yeh, Wen-Kuan; Lin, Chien-Ting; Chou, T.H.
國立成功大學 2007-02 The investigation of post-annealing-induced defects behavior on 90-nm in halo nMOSFETs with low-frequency noise and charge-pumping measuring Lai, Chieh-Ming; Fang, Yean-Kuen; Yeh, Wen-Kuan; Lin, C. T.; Chou, T. H.
國立成功大學 2007-02 A novel strain method for enhancement of 90-nm node and beyond FUSI-gated CMOS performance Lin, Chien-Ting; Fang, Yean-Kuen; Yeh, Wen-Kuan; Lee, Tung-Hsing; Chen, Ming-Shing; Lai, Chieh-Ming; Hsu, Che-Hua; Chen, Liang-Wei; Cheng, Li-Wei; Ma, Mike
國立成功大學 2006-11 The geometry effect of contact etch stop layer impact on device performance and reliability for 90-nm SOI nMOSFETs Lai, Chieh-Ming; Fang, Yean-Kuen; Lin, Chien-Ting; Yeh, Wen-Kuan
國立成功大學 2006-06 The impacts of high tensile stress CESL and geometry design on device performance and reliability for 90 nm SOI nMOSFETs Lai, Chieh-Ming; Fang, Yean-Kuen; Lin, Chien-Ting; Hsu, Chia-Wei; Yeh, Wen-Kuan
國立成功大學 2006-04 Stress technology impact on device performances and reliability for (100) sub-90 nm silicon-on-insulator complementary metal-oxide-semiconductor field-effect-transistors Lai, Chieh-Ming; Fang, Yean-Kuen; Yeh, Wen-Kuan
國立高雄大學 2006 The impact of stress enhanced technology for sub-90nm SOI MOSFETs Yeh, Wen-Kuan; Lai, Chieh-Ming; Lin, Chien-Ting; Fang, Yean-Kuen
國立成功大學 2005-04 Width effect on hot-carrier-induced degradation for 90nm partially depleted SOICMOSFETs Lai, Chieh-Ming; Fang, Yean-Kuen; Pan, Shing-Tai; Yeh, Wen-Kuan
國立高雄大學 2005 Stress technology impact on device performance and reliability for <100> sub-90nm SOI CMOSFETs Yeh, Wen-Kuan; Lai, Chieh-Ming; Lin, Chien-Ting; Fang, Yean-Kuen; Shiau, W.T.

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