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Taiwan Academic Institutional Repository >
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"lai f"
Showing items 171-180 of 455 (46 Page(s) Totally)
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| 臺大學術典藏 |
2020-04-16T02:35:16Z |
MARS: a RISC-based architecture for Lisp
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Lee, H.-C.;Lai, F.;Tsai, J.-Y.;Parng, T.-M.; Lee, H.-C.; Lai, F.; Tsai, J.-Y.; Parng, T.-M.; FEI-PEI LAI |
| 臺大學術典藏 |
2020-04-16T02:35:15Z |
HiMA: a hierarchical and modular ATM switch with partially shared output buffer
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Yu, K.; Lai, F.; FEI-PEI LAI; Tsai, Z.; Tsai, Z.;Yu, K.;Lai, F. |
| 臺大學術典藏 |
2020-04-16T02:35:15Z |
ARES-architecture reinforcing superscalar
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Lin, Y.-H.; Lai, F.; Chang, M.-C.; FEI-PEI LAI |
| 臺大學術典藏 |
2020-04-16T02:35:15Z |
A memory management unit and cache controller for the MARS system
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Lai, F.;Wu, C.-Y.;Parng, T.-M.; Lai, F.; Wu, C.-Y.; Parng, T.-M.; FEI-PEI LAI |
| 臺大學術典藏 |
2020-04-16T02:35:15Z |
Optimization on instruction reorganization
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Lai, F.;Lee, H.-C.;Lee, C.-L.; Lai, F.; Lee, H.-C.; Lee, C.-L.; FEI-PEI LAI |
| 臺大學術典藏 |
2020-04-16T02:35:14Z |
A superscalar micro-architecture supporting aggressive instruction scheduling
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Chang, M.-C.;Lai, F.; Chang, M.-C.; Lai, F.; FEI-PEI LAI |
| 臺大學術典藏 |
2020-04-16T02:35:14Z |
The complementary relationship of interprocedural register allocation and inlining
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Lai, F.;Chao, Y.-k.;Hsieh, C.-J.; Lai, F.; Chao, Y.-k.; Hsieh, C.-J.; FEI-PEI LAI |
| 臺大學術典藏 |
2020-04-16T02:35:13Z |
Efficient exploitation of instruction-level parallelism for superscalar processors by the conjugate register file scheme
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Chang, M.-C.; Lai, F.; FEI-PEI LAI |
| 臺大學術典藏 |
2020-04-16T02:35:13Z |
Image Shading Taking into Account Relativistic Effects
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Chang, M.-C.; Lai, F.; Chen, W.-C.; FEI-PEI LAI |
| 臺大學術典藏 |
2020-04-16T02:35:13Z |
Intelligent code migration technique for synchronisation operations on a multiprocessor
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Hwang, R.-Y.;Lai, F.; Hwang, R.-Y.; Lai, F.; FEI-PEI LAI |
Showing items 171-180 of 455 (46 Page(s) Totally)
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