|
|
Taiwan Academic Institutional Repository >
Browse by Author
|
"lai f"
Showing items 171-180 of 455 (46 Page(s) Totally) << < 13 14 15 16 17 18 19 20 21 22 > >> View [10|25|50] records per page
| 臺大學術典藏 |
2020-04-16T02:35:16Z |
MARS: a RISC-based architecture for Lisp
|
Lee, H.-C.;Lai, F.;Tsai, J.-Y.;Parng, T.-M.; Lee, H.-C.; Lai, F.; Tsai, J.-Y.; Parng, T.-M.; FEI-PEI LAI |
| 臺大學術典藏 |
2020-04-16T02:35:15Z |
HiMA: a hierarchical and modular ATM switch with partially shared output buffer
|
Yu, K.; Lai, F.; FEI-PEI LAI; Tsai, Z.; Tsai, Z.;Yu, K.;Lai, F. |
| 臺大學術典藏 |
2020-04-16T02:35:15Z |
ARES-architecture reinforcing superscalar
|
Lin, Y.-H.; Lai, F.; Chang, M.-C.; FEI-PEI LAI |
| 臺大學術典藏 |
2020-04-16T02:35:15Z |
A memory management unit and cache controller for the MARS system
|
Lai, F.;Wu, C.-Y.;Parng, T.-M.; Lai, F.; Wu, C.-Y.; Parng, T.-M.; FEI-PEI LAI |
| 臺大學術典藏 |
2020-04-16T02:35:15Z |
Optimization on instruction reorganization
|
Lai, F.;Lee, H.-C.;Lee, C.-L.; Lai, F.; Lee, H.-C.; Lee, C.-L.; FEI-PEI LAI |
| 臺大學術典藏 |
2020-04-16T02:35:14Z |
A superscalar micro-architecture supporting aggressive instruction scheduling
|
Chang, M.-C.;Lai, F.; Chang, M.-C.; Lai, F.; FEI-PEI LAI |
| 臺大學術典藏 |
2020-04-16T02:35:14Z |
The complementary relationship of interprocedural register allocation and inlining
|
Lai, F.;Chao, Y.-k.;Hsieh, C.-J.; Lai, F.; Chao, Y.-k.; Hsieh, C.-J.; FEI-PEI LAI |
| 臺大學術典藏 |
2020-04-16T02:35:13Z |
Efficient exploitation of instruction-level parallelism for superscalar processors by the conjugate register file scheme
|
Chang, M.-C.; Lai, F.; FEI-PEI LAI |
| 臺大學術典藏 |
2020-04-16T02:35:13Z |
Image Shading Taking into Account Relativistic Effects
|
Chang, M.-C.; Lai, F.; Chen, W.-C.; FEI-PEI LAI |
| 臺大學術典藏 |
2020-04-16T02:35:13Z |
Intelligent code migration technique for synchronisation operations on a multiprocessor
|
Hwang, R.-Y.;Lai, F.; Hwang, R.-Y.; Lai, F.; FEI-PEI LAI |
Showing items 171-180 of 455 (46 Page(s) Totally) << < 13 14 15 16 17 18 19 20 21 22 > >> View [10|25|50] records per page
|