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Taiwan Academic Institutional Repository >
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"lai feipei"
Showing items 196-205 of 253 (26 Page(s) Totally)
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| 臺大學術典藏 |
2003-08 |
A power-aware SWDR cell for reducing cache write power
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Chang, Y.-J. and Yang, C.-L. and Lai, F.; Chang, Yen-Jen; Yang, Chia-Lin; Lai, Feipei; Chang, Yen-Jen; Yang, Chia-Lin; Lai, Feipei |
| 國立臺灣大學 |
2003-07 |
An implementation of public key cryptosystem TTM with linear time complexity for decryption
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Hu, Yuh-Hua; Wang, Lih-Chung; Chen, Jiun-Ming; Lai, Feipei; Chou, Chun-Yen |
| 國立臺灣大學 |
2003-06 |
E-Vanguard for Emergency - a wireless system for rescue and healthcare
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Chen, Shun-Chuan; Chen, Hsuan-Wei; Lee, Ang; Chao, Kuo-Hao; Huang, Yu-Cheng; Lai, Feipei |
| 國立臺灣大學 |
2003 |
Design and Analysis of Low Power Cache using Two-Level Filter Scheme
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Chang, Yen-Jen; Ruan, Shanq-Jang; Lai, Feipei |
| 臺大學術典藏 |
2003 |
A power-aware SWDR cell for reducing cache write power.
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CHIA-LIN YANG; Lai, Feipei; Yang, Chia-Lin; Chang, Yen-Jen |
| 國立臺灣大學 |
2002-11 |
A distributed key management protocol for dynamic groups
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Lin, Jen-Chiun; Chou, Chun-Yen; Lai, Feipei; Wu, Kuen-Pin |
| 國立臺灣大學 |
2002-10 |
Paged cache: an efficient partition architecture for reducing power, area and access time
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Chang, Yen-Jen; Lai, Feipei |
| 國立臺灣大學 |
2002-10 |
Energy analysis of bipartition architecture for pipelined circuits
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Ruan, Shanq-Jang; Naroska, Edwin; Chang, Yen-Ren; Ho, Chia-Lin; Lai, Feipei |
| 國立臺灣大學 |
2002-09 |
Cache design for eliminating the address translation bottleneck and reducing the tag area cost
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Chang, Yen-Jen; Lai, Feipei; Ruan, Shanq-Jang |
| 國立臺灣大學 |
2002-09 |
Power analysis of bipartition and dual-encoding architecture for pipelined circuits
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Ruan, Shanq-Jang; Ho, Chia-Lin; Naroska, Edwin; Lai, Feipei |
Showing items 196-205 of 253 (26 Page(s) Totally)
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