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Showing items 201-210 of 253 (26 Page(s) Totally)
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| 國立臺灣大學 |
2002-11 |
A distributed key management protocol for dynamic groups
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Lin, Jen-Chiun; Chou, Chun-Yen; Lai, Feipei; Wu, Kuen-Pin |
| 國立臺灣大學 |
2002-10 |
Paged cache: an efficient partition architecture for reducing power, area and access time
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Chang, Yen-Jen; Lai, Feipei |
| 國立臺灣大學 |
2002-10 |
Energy analysis of bipartition architecture for pipelined circuits
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Ruan, Shanq-Jang; Naroska, Edwin; Chang, Yen-Ren; Ho, Chia-Lin; Lai, Feipei |
| 國立臺灣大學 |
2002-09 |
Cache design for eliminating the address translation bottleneck and reducing the tag area cost
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Chang, Yen-Jen; Lai, Feipei; Ruan, Shanq-Jang |
| 國立臺灣大學 |
2002-09 |
Power analysis of bipartition and dual-encoding architecture for pipelined circuits
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Ruan, Shanq-Jang; Ho, Chia-Lin; Naroska, Edwin; Lai, Feipei |
| 國立臺灣大學 |
2002 |
ENPCO: An Entropy-Based Partition-Codec Algorithm to Reduce Power for bipartition-codec architecture in Pipelined Circuits
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Ruan, Shanq-Jang; Naroska, Edwin; Chang, Yen-Jen; Lai, Feipei; Schwiegelshohn, Uwe |
| 國立臺灣大學 |
2001-11 |
A constant size rekeying message framework for secure multicasting
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Tseng, Chih-Kuang; Wu, Kuen-Pin; Lin, Jen-Chiun; Chou, Chun-Yen; Lai, Feipei |
| 國立臺灣大學 |
2001-06 |
Multimedia ASIP SoC codesign based on multicriteria optimization
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Jeng, I-Horng; Lai, Feipei; Naroska, Edwin; Schwiegelshohn, Uwe |
| 國立臺灣大學 |
2001-05 |
Synthesis of partition-codec architecture for low power and small area circuit design
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Ruan, Shanq-Jang; Lin, Jen-Chiun; Chen, Po-Hung; Tsai, Kun-Lin; Lai, Feipei |
| 國立臺灣大學 |
2001-05 |
An entropy-based algorithm to reduce area overhead for bipartition-codec architecture
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Chen, Po-Hung; Ruan, Shanq-Jang; Wu, Kuen-Pin; Hu, Dai-Xun; Lai, Feipei; Tsai, Kun-Lin |
Showing items 201-210 of 253 (26 Page(s) Totally)
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