| 國立臺灣大學 |
2002 |
ENPCO: An Entropy-Based Partition-Codec Algorithm to Reduce Power for bipartition-codec architecture in Pipelined Circuits
|
Ruan, Shanq-Jang; Naroska, Edwin; Chang, Yen-Jen; Lai, Feipei; Schwiegelshohn, Uwe |
| 國立臺灣大學 |
2001-11 |
A constant size rekeying message framework for secure multicasting
|
Tseng, Chih-Kuang; Wu, Kuen-Pin; Lin, Jen-Chiun; Chou, Chun-Yen; Lai, Feipei |
| 國立臺灣大學 |
2001-06 |
Multimedia ASIP SoC codesign based on multicriteria optimization
|
Jeng, I-Horng; Lai, Feipei; Naroska, Edwin; Schwiegelshohn, Uwe |
| 國立臺灣大學 |
2001-05 |
Synthesis of partition-codec architecture for low power and small area circuit design
|
Ruan, Shanq-Jang; Lin, Jen-Chiun; Chen, Po-Hung; Tsai, Kun-Lin; Lai, Feipei |
| 國立臺灣大學 |
2001-05 |
An entropy-based algorithm to reduce area overhead for bipartition-codec architecture
|
Chen, Po-Hung; Ruan, Shanq-Jang; Wu, Kuen-Pin; Hu, Dai-Xun; Lai, Feipei; Tsai, Kun-Lin |
| 國立臺灣大學 |
2001 |
Hierarchical Access Control Using the Secure Filter
|
Wu, Kuen-Pin; Ruan, Shanq-Jang; Tseng, Chih-Kuang; Lai, Feipei |
| 國立臺灣大學 |
2001 |
Efficient parallel timing simulation of synchronous models on networks of workstations
|
Naroska, Edwin; Lai, Feipei; Shang, Rung-Ji; Schwiegelshohn, Uwe |
| 國立臺灣大學 |
2001 |
A Bipartition-Codec Architecture to Reduce Power in Pipelined Circuits
|
Ruan, Shanq-Jang; Shang, Rung-Ji; Lai, Feipei; Tsai, Kun-Lin |
| 國立臺灣大學 |
2000-12 |
An effective output-oriented algorithm for low power multipartition architecture
|
Ruan, Shanq-Jang; Lin, Jen-Chiun; Chen, Po-Hung; Lai, Feipei; Tsai, Kun-Lin; Yu, Chung-Wei |
| 國立臺灣大學 |
2000-11 |
On key distribution in secure multicasting
|
Wu, Kuen-Pin; Ruan, Shanq-Jang; Lai, Feipei; Tseng, Chih-Kuang |
| 國立臺灣大學 |
2000 |
Performance analysis of broadcast in mobile ad hoc networks with synchronized and non-synchronized reception
|
Pan, Kuang-Hung; Wu, Hsiao-Kuang; Shang, Rung-Ji; Lai, Feipei |
| 國立臺灣大學 |
2000 |
Fast, Robust Motion Estimation Using Simulated Annealing
|
Shie, Mon-Chau; Fang, Wen-Hsien; Hung, Kuo-Jui; Lai, Feipei |
| 國立臺灣大學 |
2000 |
Multicriteria Codesign Optimization for Embedded Multimedia Communication System
|
JENG, I-Horng; LAI, Feipei |
| 國立臺灣大學 |
1999-11 |
A bipartition-codec architecture to reduce power in pipelined circuits
|
Ruan, Shanq-Jang; Shang, Rung-Ji; Lai, Feipei; Chen, Shyh-Jong; Huang, Xian-Jun |
| 國立臺灣大學 |
1999-05 |
Communications over two-way waveform channels in wireless networks
|
Pan, Kuang-Hung; Wu, Hsiao-Kuang; Shang, Rung-Ji; Lai, Feipei; Lin, Yen-Wen |
| 國立臺灣大學 |
1999-02 |
The impacts of synchronized and non-synchronized reception on broadcast in multihop radio networks
|
Pan, Kuang-Hung; Wu, Hsiao-Kuang; Shang, Rung-Ji; Lai, Feipei |
| 國立臺灣大學 |
1999 |
Multiple branch Prediction for Wide-Issue Superscalar
|
Hwang, Shu-Lin; Chen, Che-Chun; Lai, Feipei |
| 國立臺灣大學 |
1999 |
Commit Protocol for Lower-Powered Mobile Clients
|
Lin, Yen-Wen; Wu, Hsiao-Kuang; Lai, Feipei |
| 國立臺灣大學 |
1999 |
FACE: Fine-tuned Architecture Codesign Environment for ASIP Development
|
Jeng, I-Horng; Lai, Feipei; Tseng, Yuh-Dar |
| 國立臺灣大學 |
1997 |
Region-based template deformation and masking for eye-feature extraction and description
|
Deng, Jyh-Yuan; Lai, Feipei |
| 國立彰化師範大學 |
1996-10 |
Image Shading Taking into Account Relativistic Effects
|
Chang, Meng-chou; Lai, Feipei; Chen, Wei-chao |
| 國立彰化師範大學 |
1996-03 |
Efficient Exploitation of Instruction-Level Parallelism for Superscalar Processors by the Conjugate Register File Scheme
|
Chang, Meng-chou; Lai, Feipei |
| 國立臺灣大學 |
1995-08 |
A simple tree pattern matching algorithm for code generator
|
Chen, Tzer-Shyong; Lai, Feipei; Shang, Rung-Ji |
| 國立臺灣大學 |
1994-12 |
A performance evaluation procedure for a class of growable ATM switches
|
Tsai, Zsehong; Yu, Kangyei; Lai, Feipei |
| 臺大學術典藏 |
1994-12 |
A performance evaluation procedure for a class of growable ATM switches
|
Tsai, Zsehong; Yu, Kangyei; Lai, Feipei; Tsai, Zsehong; Yu, Kangyei; Lai, Feipei; TsaiZsehong |
| 國立臺灣大學 |
1994-05 |
The complementary relationship of interprocedural register allocation and inlining
|
Lai, Feipei; Chao, Yung-Kuang |
| 國立彰化師範大學 |
1994-03 |
A Superscalar Micro-architecture Supporting Aggressive Instruction Scheduling
|
Chang, Meng-chou; Lai, Feipei |
| 國立臺灣大學 |
1994-01 |
A pipeline bubbles reduction technique for the Monsoon dataflow architecture
|
Lai, Feipei; Tsai, Fong-Chou |
| 國立臺灣大學 |
1993-10 |
Arden - Architecture Development Environment
|
Lai, Feipei; Hwang, Shu-Lin; Chen, Tzer-Shyong; Hsieh, Chia-Rung |
| 國立彰化師範大學 |
1992-12 |
Exploiting Instruction-Level Parallelism with the Conjugate Register File Scheme
|
Chang, Meng-chou; Lai, Feipei; Shang, Rung-ji |
| 淡江大學 |
1992-11-11 |
Estimating register cost using spots
|
Lai, Feipei; Yeh, Chia-cheng; 李鴻璋; Lee, Hung-chang |
| 國立臺灣大學 |
1992-11 |
Estimating register cost using spots
|
Lai, Feipei; Yeh, Chia-Cheng; Lee, Hung-Chang |
| 淡江大學 |
1992-09-01 |
Register allocation via dynamically updated information
|
賴飛羆; Lai, Feipei; 葉家誠; Yeh, Chia-cheng; 李鴻璋; Lee, Hung-chang |
| 淡江大學 |
1992-09-01 |
動態資訊式暫存器配置法
|
賴飛羆; Lai, Feipei; 葉家誠; Yeh, Chia-cheng; 李鴻璋; Lee, Hung-chang |
| 國立彰化師範大學 |
1992-05 |
Enhancing Boosting with Semantic Register in a Superscalar Processor
|
Lai, Feipei; Chang, Meng-chou |
| 國立臺灣大學 |
1991-10 |
An intelligent trend prediction and reversal recognition system using dual-module neural networks
|
Jang, Gia-Shuh; Lai, Feipei; Jiang, Bor-Wei; Chien, Li-Hua |
| 國立臺灣大學 |
1991-09 |
Analysis of branch handling strategies under hierarchical memory system
|
Lee, Hung-Chung; Lai, Feipei |
| 國立彰化師範大學 |
1991-05 |
ARES-Architecture REinforcing Superscalar
|
Lin, Yuh-Haur; Lai, Feipei; Chang, Meng-chou |
| 國立臺灣大學 |
1991-05 |
ARES-architecture reinforcing superscalar
|
Lin, Yuh-Haur; Lai, Feipei; Chang, Meng-Chou |
| 國立臺灣大學 |
1990-11 |
A memory management unit and cache controller for the MARS system
|
Lai, Feipei; Wu, Chyuan-Yow; Parng, Tai-Ming |
| 國立臺灣大學 |
1990-11 |
Optimization on instruction reorganization
|
Lai, Feipei; Lee, Hung-Chang; Lee, Chun-Luh |
| 國立臺灣大學 |
1990-04 |
MARS performance evaluation with different interconnection networks
|
Lai, Feipei; Tzeng, Lea-Ming; Chang, Thom-Ling; Parng, Tai-Ming |
| 淡江大學 |
1990-03 |
MARS: aRISC-based architecture for Lisp
|
Lee, Hung-Chang; Lai, Feipei; Tsai, Jenn-yuan; Parng, Tai-ming |
| 國立臺灣大學 |
1990 |
MARS: a RISC-based architecture for Lisp
|
Lee, Hung-Chang; Lai, Feipei; Tsai, Jenn-Yuan; Parng, Tai-Ming |
| 國立臺灣大學 |
1989-10 |
MARS-a RISC-based architecture for LISP
|
Lee, Hung-Chang; Lai, Feipei; Tsai, Jenn-Yuan; Parng, Tai-Ming; Li, Yu-Gang |
| 國立臺灣大學 |
1989-05 |
An upper-bound algorithm for gate-level delay analysis
|
Lu, Sunshin; Lai, Feipei |
| 國立臺灣大學 |
1989-05 |
A grouping heuristic algorithm for gate matrix layout
|
Liu, Jongping; Lai, Feipei |
| 國立臺灣大學 |
1989-05 |
MARS-Multiprocessor architecture reconciling symbolic with numerical processing-a CPU ensemble with zero-delay branch/jump
|
Jang, Gia-Shuh; Lai, Feipei; Lee, Hung-Chang; Maa, Yeong-Chang; Parng, Tai-Ming; Tsai, Jenn-Yuan |
