| 國立臺灣大學 |
1994-05 |
The complementary relationship of interprocedural register allocation and inlining
|
Lai, Feipei; Chao, Yung-Kuang |
| 國立彰化師範大學 |
1994-03 |
A Superscalar Micro-architecture Supporting Aggressive Instruction Scheduling
|
Chang, Meng-chou; Lai, Feipei |
| 國立臺灣大學 |
1994-01 |
A pipeline bubbles reduction technique for the Monsoon dataflow architecture
|
Lai, Feipei; Tsai, Fong-Chou |
| 國立臺灣大學 |
1993-10 |
Arden - Architecture Development Environment
|
Lai, Feipei; Hwang, Shu-Lin; Chen, Tzer-Shyong; Hsieh, Chia-Rung |
| 國立彰化師範大學 |
1992-12 |
Exploiting Instruction-Level Parallelism with the Conjugate Register File Scheme
|
Chang, Meng-chou; Lai, Feipei; Shang, Rung-ji |
| 淡江大學 |
1992-11-11 |
Estimating register cost using spots
|
Lai, Feipei; Yeh, Chia-cheng; 李鴻璋; Lee, Hung-chang |
| 國立臺灣大學 |
1992-11 |
Estimating register cost using spots
|
Lai, Feipei; Yeh, Chia-Cheng; Lee, Hung-Chang |
| 淡江大學 |
1992-09-01 |
Register allocation via dynamically updated information
|
賴飛羆; Lai, Feipei; 葉家誠; Yeh, Chia-cheng; 李鴻璋; Lee, Hung-chang |
| 淡江大學 |
1992-09-01 |
動態資訊式暫存器配置法
|
賴飛羆; Lai, Feipei; 葉家誠; Yeh, Chia-cheng; 李鴻璋; Lee, Hung-chang |
| 國立彰化師範大學 |
1992-05 |
Enhancing Boosting with Semantic Register in a Superscalar Processor
|
Lai, Feipei; Chang, Meng-chou |
| 國立臺灣大學 |
1991-10 |
An intelligent trend prediction and reversal recognition system using dual-module neural networks
|
Jang, Gia-Shuh; Lai, Feipei; Jiang, Bor-Wei; Chien, Li-Hua |
| 國立臺灣大學 |
1991-09 |
Analysis of branch handling strategies under hierarchical memory system
|
Lee, Hung-Chung; Lai, Feipei |
| 國立彰化師範大學 |
1991-05 |
ARES-Architecture REinforcing Superscalar
|
Lin, Yuh-Haur; Lai, Feipei; Chang, Meng-chou |
| 國立臺灣大學 |
1991-05 |
ARES-architecture reinforcing superscalar
|
Lin, Yuh-Haur; Lai, Feipei; Chang, Meng-Chou |
| 國立臺灣大學 |
1990-11 |
A memory management unit and cache controller for the MARS system
|
Lai, Feipei; Wu, Chyuan-Yow; Parng, Tai-Ming |
| 國立臺灣大學 |
1990-11 |
Optimization on instruction reorganization
|
Lai, Feipei; Lee, Hung-Chang; Lee, Chun-Luh |
| 國立臺灣大學 |
1990-04 |
MARS performance evaluation with different interconnection networks
|
Lai, Feipei; Tzeng, Lea-Ming; Chang, Thom-Ling; Parng, Tai-Ming |
| 淡江大學 |
1990-03 |
MARS: aRISC-based architecture for Lisp
|
Lee, Hung-Chang; Lai, Feipei; Tsai, Jenn-yuan; Parng, Tai-ming |
| 國立臺灣大學 |
1990 |
MARS: a RISC-based architecture for Lisp
|
Lee, Hung-Chang; Lai, Feipei; Tsai, Jenn-Yuan; Parng, Tai-Ming |
| 國立臺灣大學 |
1989-10 |
MARS-a RISC-based architecture for LISP
|
Lee, Hung-Chang; Lai, Feipei; Tsai, Jenn-Yuan; Parng, Tai-Ming; Li, Yu-Gang |
| 國立臺灣大學 |
1989-05 |
An upper-bound algorithm for gate-level delay analysis
|
Lu, Sunshin; Lai, Feipei |
| 國立臺灣大學 |
1989-05 |
A grouping heuristic algorithm for gate matrix layout
|
Liu, Jongping; Lai, Feipei |
| 國立臺灣大學 |
1989-05 |
MARS-Multiprocessor architecture reconciling symbolic with numerical processing-a CPU ensemble with zero-delay branch/jump
|
Jang, Gia-Shuh; Lai, Feipei; Lee, Hung-Chang; Maa, Yeong-Chang; Parng, Tai-Ming; Tsai, Jenn-Yuan |
