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Showing items 1-23 of 23 (1 Page(s) Totally)
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| 臺大學術典藏 |
2020-06-11T07:06:12Z |
Tutorial: "Design of high-speed wireline transceivers".
|
Lee, Jri; Lee, Jri; JRI LEE |
| 臺大學術典藏 |
2020-06-11T07:06:10Z |
A 2 x 25-Gb/s Receiver With 2:5 DMUX for 100-Gb/s Ethernet
|
Wu, Ke-Chung;Lee, Jri; Wu, Ke-Chung; Lee, Jri; JRI LEE |
| 臺大學術典藏 |
2020-06-11T07:06:10Z |
W-Band BPSK and QPSK Transceivers With Costas-Loop Carrier Recovery in 65-nm CMOS Technology
|
Huang, Shih-Jou;Yeh, Yu-Ching;Wang, Huaide;Chen, Pang-Ning;Lee, Jri; Huang, Shih-Jou; Yeh, Yu-Ching; Wang, Huaide; Chen, Pang-Ning; Lee, Jri; JRI LEE |
| 臺大學術典藏 |
2020-06-11T07:06:09Z |
Study of Subharmonically Injection-Locked PLLs
|
Lee, Jri;Wang, Huaide; Lee, Jri; Wang, Huaide; JRI LEE |
| 臺大學術典藏 |
2020-06-11T07:06:09Z |
A 20-Gb/s Full-Rate Linear Clock and Data Recovery Circuit With Automatic Frequency Acquisition
|
Lee, Jri;Wu, Ke-Chung; Lee, Jri; Wu, Ke-Chung; JRI LEE |
| 臺大學術典藏 |
2020-06-11T07:06:05Z |
A 20Gb/s Duobinary Transceiver in 90nm CMOS.
|
Lee, Jri;Chen, Ming-Shuan;Wang, Huaide; Lee, Jri; Chen, Ming-Shuan; Wang, Huaide; JRI LEE |
| 臺大學術典藏 |
2010 |
A Fully-Integrated 77-GHz FMCW Radar Transceiver in 65-nm CMOS Technology
|
Lee, Jri;Li, Yi-An;Hung, Meng-Hsiung;Huang, Shih-Jou; Lee, Jri; Li, Yi-An; Hung, Meng-Hsiung; Huang, Shih-Jou; JRI LEE |
| 國立臺灣大學 |
2008-09 |
Design and Comparison of Three 20-Gb/s Backplane Transceivers for Duobinary
|
Lee, Jri; Chen, M.; Wang, H. |
| 國立臺灣大學 |
2008-06 |
A 75-GHz Phase-Locked Loop in 90-nm CMOS Technique
|
Lee, Jri; Liu, M.; Wang, H. |
| 國立臺灣大學 |
2008-03 |
A 20-Gb/s Burst-Mode Clock and Data Recovery Circuit Using Injection-Locking Technique
|
Lee, Jri; Liu, M. |
| 國立臺灣大學 |
2008 |
A 20-Gb/s Burst-Mode Clock and Data Recovery Circuit Using Injection-Locking Technique
|
Lee, Jri; Liu, Mingchung |
| 國立臺灣大學 |
2008 |
A 75-GHz Phase-Locked Loop in 90-nm CMOS Technology
|
Lee, Jri; Liu, Mingchung; Wang, Huaide |
| 國立臺灣大學 |
2008 |
Design and Comparison of Three 20-Gb/s Backplane Transceivers for Duobinary, PAM4, and NRZ Data
|
Lee, Jri; Chen, Ming-Shuan; Wang, Huai-De |
| 國立臺灣大學 |
2006-09 |
A 20-Gb/s Adaptive Equalizer in 0.13 um CMOS Technology
|
Lee, Jri |
| 臺大學術典藏 |
2006-09 |
A 20-Gb/s Adaptive Equalizer in 0.13 um CMOS Technology
|
Lee, Jri; Lee, Jri |
| 國立臺灣大學 |
2006 |
A 3-to-8-GHz fast-hopping frequency synthesizer in 0.18-μm CMOS technology
|
Lee, Jri |
| 國立臺灣大學 |
2006 |
High-Speed Circuit Designs for Transmitters in Broadband Data Links
|
Lee, Jri |
| 國立臺灣大學 |
2006 |
A 20-Gb/s Adaptive Equalizer in 0.13-μm CMOS Technology
|
Lee, Jri |
| 國立臺灣大學 |
2005-06 |
A 20-Gb/s 2-to-1 MUX and a 40-GHz VCO in 0.18-/spl mu/m CMOS technology
|
Lee, Jri; Ding, Jian-Yu; Cheng, Tuan-Yi |
| 國立臺灣大學 |
2005-06 |
Design and analysis of a 20-GHz clock multiplication unit in 0.18-/spl mu/m CMOS technology
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Lee, Jri; Wu, Shanghann |
| 國立臺灣大學 |
2005-02 |
A 7-band 3-8 GHz frequency synthesizer with 1 ns band-switching time in 0.18 /spl mu/m CMOS technology
|
Lee, Jri; Chiu, Da-Wei |
| 國立臺灣大學 |
2004-04 |
A 40-GHz Frequency Divider in 0.18-m CMOS Technology
|
Lee, Jri; Razavi, Behzad |
| 國立臺灣大學 |
2004 |
Analysis and Modeling of Bang-Bang Clock and Data Recovery Circuits
|
Lee, Jri; Kundert, K.S.; Razavi, B. |
Showing items 1-23 of 23 (1 Page(s) Totally)
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