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Institution Date Title Author
國立交通大學 2015-07-21T11:20:45Z Fabrication of High-Performance Poly-Si Thin-Film Transistors With Sub-Lithographic Channel Dimensions Lee, Ko-Hui; Lin, Horng-Chih; Huang, Tiao-Yuan
國立交通大學 2014-12-12T02:39:02Z 新穎多晶矽奈米線非揮發性記憶體之研製與分析 李克慧; Lee, Ko-Hui; 林鴻志; 黃調元; Lin, Horng-Chih; Huang, Tiao-Yuan
國立交通大學 2014-12-08T15:36:25Z Fabrication of tri-gated junctionless poly-Si transistors with I-line based lithography Lin, Cheng-I; Lee, Ko-Hui; Lin, Horng-Chih; Huang, Tiao-Yuan
國立交通大學 2014-12-08T15:36:25Z Gate-all-around floating-gate memory device with triangular poly-Si nanowire channels Tsai, Jung-Ruey; Lee, Ko-Hui; Lin, Horng-Chih; Huang, Tiao-Yuan
國立交通大學 2014-12-08T15:35:08Z Novel gate-all-around polycrystalline silicon nanowire memory device with HfAlO charge-trapping layer Lee, Ko-Hui; Lin, Horng-Chih; Huang, Tiao-Yuan
國立交通大學 2014-12-08T15:32:59Z Low-voltage high-speed programming/erasing floating-gate memory device with gate-all-around polycrystalline silicon nanowire Lee, Ko-Hui; Tsai, Jung-Ruey; Chang, Ruey-Dar; Lin, Horng-Chih; Huang, Tiao-Yuan
國立交通大學 2014-12-08T15:30:52Z Impacts of Nanocrystal Location on the Operation of Trap-Layer-Engineered Poly-Si Nanowired Gate-All-Around SONOS Memory Devices Luo, Cheng-Wei; Lin, Horng-Chih; Lee, Ko-Hui; Chen, Wei-Chen; Hsu, Hsing-Hui; Huang, Tiao-Yuan
國立交通大學 2014-12-08T15:30:35Z Novel Method for Fabrication of Tri-Gated Poly-Si Nanowire Field-Effect Transistors With Sublithographic Channel Dimensions Lee, Ko-Hui; Lin, Horng-Chih; Huang, Tiao-Yuan
國立交通大學 2014-12-08T15:29:51Z A Novel Charge-Trapping-Type Memory With Gate-All-Around Poly-Si Nanowire and HfAlO Trapping Layer Lee, Ko-Hui; Lin, Horng-Chih; Huang, Tiao-Yuan
國立交通大學 2014-12-08T15:10:06Z Performance Improvement of Polycrystalline Silicon Nanowire Thin-Film Transistors by a High-k Capping Layer Lee, Ko-Hui; Hsu, Hsing-Hui; Lin, Horng-Chih; Huang, Tiao-Yuan

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