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Showing items 1-11 of 11 (1 Page(s) Totally)
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| 國立交通大學 |
2018-08-21T05:56:53Z |
On Routing Fixed Escaped Boundary Pins for High Speed Boards
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Tsai, Tsung-Ying; Lee, Ren-Jie; Chin, Ching-Yu; Kuan, Chung-Yi; Chen, Hung-Ming; Kajitani, Yoji |
| 國立交通大學 |
2018-08-21T05:56:51Z |
Area-I/O RDL Routing for Chip-Package Codesign Considering Regional Assignment
|
Lin, Kun-Sheng; Hsu, Hsin-Wu; Lee, Ren-Jie; Chen, Hung-Ming |
| 國立交通大學 |
2014-12-16T06:15:25Z |
Pin-out Designation Method for Package-Board Codesign
|
Lee, Ren-Jie; Chen, Hung-Ming |
| 國立交通大學 |
2014-12-16T06:14:09Z |
Pin-out designation method for package-board codesign
|
Lee Ren-Jie; Chen Hung-Ming |
| 國立交通大學 |
2014-12-12T01:24:38Z |
晶片—封裝—印刷電路板共同設計之演算法
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李仁傑; Lee, Ren-Jie; 陳宏明; Chen, Hung-Ming |
| 國立交通大學 |
2014-12-08T15:31:02Z |
Board- and Chip-Aware Package Wire Planning
|
Lee, Ren-Jie; Hsu, Hsin-Wu; Chen, Hung-Ming |
| 國立交通大學 |
2014-12-08T15:30:24Z |
A Study of Row-Based Area-Array I/O Design Planning in Concurrent Chip-Package Design Flow
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Lee, Ren-Jie; Chen, Hung-Ming |
| 國立交通大學 |
2014-12-08T15:21:18Z |
Row-Based Area-Array I/O Design Planning in Concurrent Chip-Package Design Flow
|
Lee, Ren-Jie; Chen, Hung-Ming |
| 國立交通大學 |
2014-12-08T15:12:59Z |
Fast flip-chip pin-out designation respin by pin-block design and floorplanning for package-board codesign
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Lee, Ren-Jie; Lai, Ming-Fang; Chen, Hung-Ming |
| 國立交通大學 |
2014-12-08T15:11:40Z |
Efficient Package Pin-Out Planning With System Interconnects Optimization for Package-Board Codesign
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Lee, Ren-Jie; Chen, Hung-Ming |
| 國立交通大學 |
2014-12-08T15:09:03Z |
Fast Flip-Chip Pin-Out Designation Respin for Package-Board Codesign
|
Lee, Ren-Jie; Chen, Hung-Ming |
Showing items 1-11 of 11 (1 Page(s) Totally)
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