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Showing items 1-4 of 4 (1 Page(s) Totally)
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| 國立交通大學 |
2020-07-01T05:21:18Z |
Nitride Induced Stress Affecting Crystallinity of Sidewall Damascene Gate-All-Around Nanowire Poly-Si FETs
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Shen, Chuan-Hui; Chen, Wei-Yen; Lee, Shen-Yang; Ku, Po-Yi; Chao, Tien-Sheng |
| 國立交通大學 |
2020-02-01 |
Effect of Seed Layer on Gate-All-Around Poly-Si Nanowire Negative-Capacitance FETs With MFMIS and MFIS Structures: Planar Capacitors to 3-D FETs
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Chao, Tien-Sheng; Chen, Hsin-Yu; Huang, Yu-En; Chung, Chun-Chih; Shen, Chiuan-Huei; Kuo, Po-Yi; Lee, Shen-Yang; Chen, Han-Wei |
| 國立交通大學 |
2020-01-02T00:03:25Z |
Experimental Demonstration of Performance Enhancement of MFMIS and MFIS for 5-nm x 12.5-nm Poly-Si Nanowire Gate-All-Around Negative Capacitance FETs Featuring Seed-Layer and PMA-Free Process
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Lee, Shen-Yang; Chen, Han-Wei; Shen, Chiuan-Huei; Kuo, Po-Yi; Chung, Chun-Chih; Huang, Yu-En; Chen, Hsin-Yu; Chao, Tien-Sheng |
| 國立交通大學 |
2019-12-13T01:12:24Z |
Experimental Demonstration of Stacked Gate- All-Around Poly-Si Nanowires Negative Capacitance FETs With Internal Gate Featuring Seed Layer and Free of Post-Metal Annealing Process
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Lee, Shen-Yang; Chen, Han-Wei; Shen, Chiuan-Huei; Kuo, Po-Yi; Chung, Chun-Chih; Huang, Yu-En; Chen, Hsin-Yu; Chao, Tien-Sheng |
Showing items 1-4 of 4 (1 Page(s) Totally)
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