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"lee tgy"
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| 國立交通大學 |
2014-12-08T15:45:20Z |
An empirical three-dimensional crossover capacitance model for multilevel interconnect VLSI circuits
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Wong, SC; Lee, TGY; Ma, DJ; Chao, CJ |
| 國立交通大學 |
2014-12-08T15:43:09Z |
Generalized interconnect delay time and crosstalk models: I. Applications of interconnect optimization design
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Lee, TGY; Tseng, TY; Wong, SC; Yang, CJ; Liang, MS; Cheng, HC |
| 國立交通大學 |
2014-12-08T15:43:09Z |
Generalized interconnect delay time and crosstalk models: II. Crosstalk-induced delay time deterioration and worst crosstalk models
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Lee, TGY; Tseng, TY; Wong, SC; Yang, CJ; Liang, MS; Cheng, HC |
Showing items 1-3 of 3 (1 Page(s) Totally)
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