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| 臺大學術典藏 |
2018-09-10T05:15:50Z |
VLSI architecture for radix-2k Viterbi decoding with transpose algorithm
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Lee, Wen-Ta;Chen, Thou-Ho;Chen, Liang-Gee; Lee, Wen-Ta; Chen, Thou-Ho; Chen, Liang-Gee; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T04:47:23Z |
Radix-2k Viterbi decoding with transpose path metric processor
|
Lee, Wen-Ta;Chen, Thou-Ho;Chen, Liang-Gee; Lee, Wen-Ta; Chen, Thou-Ho; Chen, Liang-Gee; LIANG-GEE CHEN |
| 國立交通大學 |
2014-12-08T15:30:06Z |
High-Performance 0.6V V-MIN 55nm 1.0Mb 6T SRAM with Adaptive BL Bleeder
|
Yang, Hao-I; Lin, Yi-Wei; Hsia, Mao-Chih; Lin, Geng-Cing; Chang, Chi-Shin; Chen, Yin-Nien; Chuang, Ching-Te; Hwang, Wei; Jou, Shyh-Jye; Lien, Nan-Chun; Li, Hung-Yu; Lee, Kuen-Di; Shih, Wei-Chiang; Wu, Ya-Ping; Lee, Wen-Ta; Hsu, Chih-Chiang |
| 國立交通大學 |
2014-12-08T15:21:19Z |
A High-Performance Low V(MIN) 55nm 512Kb Disturb-Free 8T SRAM with Adaptive VVSS Control
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Yang, Hao-I; Yang, Shih-Chi; Hsia, Mao-Chih; Lin, Yung-Wei; Lin, Yi-Wei; Chen, Chien-Hen; Chang, Chi-Shin; Lin, Geng-Cing; Chen, Yin-Nien; Chuang, Ching-Te; Hwang, Wei; Jou, Shyh-Jye; Lien, Nan-Chun; Li, Hung-Yu; Lee, Kuen-Di; Shih, Wei-Chiang; Wu, Ya-Ping; Lee, Wen-Ta; Hsu, Chih-Chiang |
| 國立臺灣大學 |
1995-06 |
A VLSI architecture for radix-2k Viterbi decoding with transpose algorithm
|
Lee, Wen-Ta; Chen, Thou-Ho; Chen, Liang-Gee |
| 臺大學術典藏 |
1995-06 |
A VLSI architecture for radix-2k Viterbi decoding with transpose algorithm
|
Lee, Wen-Ta; Chen, Thou-Ho; Chen, Liang-Gee; Lee, Wen-Ta; Chen, Thou-Ho; Chen, Liang-Gee |
| 國立臺灣大學 |
1994-12 |
The radix-2k Viterbi decoding with transpose path metric processor
|
Lee, Wen-Ta; Chen, Thou-Ho; Chen, Liang-Gee |
| 臺大學術典藏 |
1994-12 |
The radix-2k Viterbi decoding with transpose path metric processor
|
Lee, Wen-Ta; Chen, Thou-Ho; Chen, Liang-Gee; Lee, Wen-Ta; Chen, Thou-Ho; Chen, Liang-Gee |
Showing items 1-8 of 8 (1 Page(s) Totally)
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