|
English
|
正體中文
|
简体中文
|
Total items :0
|
|
Visitors :
52746930
Online Users :
680
Project Commissioned by the Ministry of Education
Project Executed by National Taiwan University Library
|
|
|
|
Taiwan Academic Institutional Repository >
Browse by Author
|
"li fan min"
Showing items 1-10 of 14 (2 Page(s) Totally)
1 2 > >>
View [10|25|50] records per page
| 國立臺灣大學 |
2008 |
Unified Convolutional/Turbo Decoder Design Using Tile-Based Timing Analysis of VA/MAP Kernel
|
Li, Fan-Min; Lin, Cheng-Hung; Wu, An-Yeu |
| 臺大學術典藏 |
2007-04-19T04:55:08Z |
A new stopping criterion for efficient early termination in turbo decoder designs
|
Li, F.-M. and Wu, A.-Y.; Li, Fan-Min; Wu, An-Yeu; Li, Fan-Min; Wu, An-Yeu |
| 國立臺灣大學 |
2007 |
整合型錯誤更正碼之演算法及積體電路架構設計
|
李芳明; Li, Fan-Min |
| 國立臺灣大學 |
2007 |
On The New Stopping Criteria of Iterative Turbo Decoding by Using Decoding Threshold
|
Li, Fan-Min; Wu, An-Yeu |
| 國立臺灣大學 |
2006 |
High-Performance VLSI Architecture of Decision Feedback Equalizer for Gigabit Systems
|
Lin, Chih-Hsiu; Wu, An-Yeu; Li, Fan-Min |
| 國立臺灣大學 |
2005-12 |
A new stopping criterion for efficient early termination in turbo decoder designs
|
Li, Fan-Min; Wu, An-Yeu |
| 國立臺灣大學 |
2004-12 |
Unified convolutional/turbo decoder architecture design based on triple-mode MAP/VA kernel
|
Li, Fan-Min; Shen, Pei-Ling; Wu, An-Yeu |
| 臺大學術典藏 |
2004-12 |
Unified convolutional/turbo decoder architecture design based on triple-mode MAP/VA kernel
|
Li, Fan-Min; Shen, Pei-Ling; Wu, An-Yeu; Li, Fan-Min; Shen, Pei-Ling; Wu, An-Yeu |
| 國立臺灣大學 |
2004-05 |
VLSI design of dual-mode Viterbi/turbo decoder for 3GPP
|
Huang, Kai; Li, Fan-Min; Shen, Pei-Ling; Wu, An-Yeu |
| 臺大學術典藏 |
2004-05 |
VLSI design of dual-mode Viterbi/turbo decoder for 3GPP
|
Huang, Kai; Li, Fan-Min; Shen, Pei-Ling; Wu, An-Yeu; Huang, Kai; Li, Fan-Min; Shen, Pei-Ling; Wu, An-Yeu |
Showing items 1-10 of 14 (2 Page(s) Totally)
1 2 > >>
View [10|25|50] records per page
|
