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"li j c m"的相關文件
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| 臺大學術典藏 |
2019-04-22T05:22:34Z |
Efficient multi-layer obstacle-avoiding region-to-region rectilinear steiner tree construction
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Jiang, J.-H.R.;Li, J.C.M.;Pai, Y.-C.;Wen, H.-T.;Wang, J.-J.;Pai, C.-C.;Wang, R.-Y.;Chang, Y.-W.; Wang, R.-Y.; Pai, C.-C.; Wang, J.-J.; Wen, H.-T.; Pai, Y.-C.; Chang, Y.-W.; Li, J.C.M.; Jiang, J.-H.R. |
| 臺大學術典藏 |
2018-09-10T08:34:44Z |
An accurate timing-aware diagnosis algorithm for multiple small delay defects
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Chen, P.-J.;Hsu, W.-L.;Li, J.C.-M.;Tseng, N.-H.;Chen, K.-Y.;Changchien, W.-P.;Liu, C.C.C.; Chen, P.-J.; Hsu, W.-L.; Li, J.C.-M.; Tseng, N.-H.; Chen, K.-Y.; Changchien, W.-P.; Liu, C.C.C.; WEI-LI HSU; CHIEN-MO LI |
| 臺大學術典藏 |
2018-09-10T08:19:10Z |
CSER: BISER-based concurrent soft-error resilience
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Laung-Terng Wang;Touba, N.A.;Zhigang Jiang;Shianling Wu;Jiun-Lang Huang;Li, J.C.-M.; Laung-Terng Wang; Touba, N.A.; Zhigang Jiang; Shianling Wu; Jiun-Lang Huang; Li, J.C.-M.; CHIEN-MO LI; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T08:19:10Z |
Static timing analysis for flexible TFT circuits
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Chao-Hsuan Hsu;Liu, C.;En-Hua Ma;Li, J.C.-M.; Chao-Hsuan Hsu; Liu, C.; En-Hua Ma; Li, J.C.-M.; CHIEN-MO LI |
| 臺大學術典藏 |
2018-09-10T08:14:25Z |
Reliability screening of a-Si TFT circuits: Very-low voltage and I DDQ Testing
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Shen, S.-T.;Liu, C.;Ma, E.-H.;Cheng, I.-C.;Li, J.C.-M.; Shen, S.-T.; Liu, C.; Ma, E.-H.; Cheng, I.-C.; Li, J.C.-M.; I-CHUN CHENG; CHIEN-MO LI |
| 臺大學術典藏 |
2018-09-10T07:36:19Z |
Very-low-voltage testing of amorphous silicon TFT circuits
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Shen, S.-T.;Liu, W.-H.;Ma, E.-H.;Li, J.C.-M.;Cheng, I.-C.; Shen, S.-T.; Liu, W.-H.; Ma, E.-H.; Li, J.C.-M.; Cheng, I.-C.; I-CHUN CHENG |
| 臺大學術典藏 |
2018-09-10T05:29:21Z |
Diagnosis of Single stuck-at Faults and Multiple Timing Faults in Scan Chains
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Li, J. C.-M.; CHIEN-MO LI |
| 臺大學術典藏 |
2018-09-10T05:29:21Z |
Diagnosis of Resistive and Stuck-open Defects in Digital CMOS IC
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Li, J. C.-M.; E. J. McCluskey; CHIEN-MO LI |
| 臺大學術典藏 |
2018-09-10T05:29:21Z |
Diagnosis of Multiple Hold-time and Setup-time Faults in Scan Chains
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Li, J. C. M.; CHIEN-MO LI |
| 臺大學術典藏 |
2018-09-10T04:59:51Z |
A Design for Testability Technique for Low Power Delay Fault Testing
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Li, J. C. M.; CHIEN-MO LI |
顯示項目 21-30 / 40 (共4頁)
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