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"li james chien mo"的相关文件
显示项目 11-20 / 20 (共1页)
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| 臺大學術典藏 |
2018-09-10T08:47:24Z |
A Parallel Test Pattern Generation Algorithm to Meet Multiple Quality Objectives
|
Liao, Kuan-Yu; Chang, Chia-Yuan; Li, James Chien-Mo; CHIEN-MO LI |
| 國立臺灣大學 |
2008 |
Survey of Scan Chain Diagnosis
|
Huang, Yu; Guo, Ruifeng; Cheng, Wu-Tung; Li, James Chien-Mo |
| 國立臺灣大學 |
2008 |
Effective and Economic Phase Noise Testing for Single-Chip TV Tuners
|
Li, James Chien-Mo; Lin, Po-Chou; Chiang, Chih-Ming; Pan, Chuo-Jan; Tseng, Chao-Wen |
| 國立臺灣大學 |
2007 |
Column Parity Row Selection (CPRS) BIST Diagnosis Technique: Modeling and Analysis
|
Li, James Chien-Mo; Lin, Hung-Mao; Wang, Fang-Min |
| 國立臺灣大學 |
2007 |
Design and Chip Implementation of the Segment Weighted Random BIST for Low Power Testing
|
Lee, Chun-Yi; Li, James Chien-Mo |
| 國立臺灣大學 |
2005 |
Diagnosis of Timing Faults in Scan Chains Using Single Excitation Patterns
|
Li, James Chien-Mo |
| 國立臺灣大學 |
2005 |
Diagnosis of Single stuck-at Faults and Multiple Timing Faults in Scan Chains
|
Li, James Chien-Mo |
| 國立臺灣大學 |
2005 |
Diagnosis of Multiple Hold-time and Setup-time Faults in Scan Chains
|
Li, James Chien-Mo |
| 國立臺灣大學 |
2005 |
Diagnosis of Resistive-Open and Stuck-Open Defects in Digital CMOS ICs
|
Li, James Chien-Mo; McCluskey, Edward J. |
| 國立臺灣大學 |
2004 |
A Design for Testability Technique for Low Power Delay Fault Testing
|
Li, James Chien-Mo |
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