| 國立交通大學 |
2014-12-12T01:34:14Z |
以區域為基礎的整數線性規劃軌道繞線
|
林怡君; Lin, Yi-chun; 李毅郎; Li, Yih-Lang |
| 國立交通大學 |
2014-12-12T01:33:54Z |
以階層為基礎插入緩衝器的時鐘樹合成
|
陳繪琦; Chen, Hui-Chi; 李毅郎; Li, Yih-Lang |
| 國立交通大學 |
2014-12-12T01:33:50Z |
KDL: 應用群聚法考慮時脈限制的結構化特定應用積體電路配置器
|
高志承; Kao, Chih-Cheng; 李毅郎; Li, Yih-Lang |
| 國立交通大學 |
2014-12-12T01:24:09Z |
在奈米設計繞線中針對效率,可製造性與良率的最佳化
|
林彥宏; Lin, Yen-Hung; 李毅郎; Li, Yih-Lang |
| 國立交通大學 |
2014-12-12T01:19:13Z |
考慮冗餘接點之電路線軌指派法
|
蘇冠丞; Su, Guan-Chan; 李毅郎; Li, Yih-Lang |
| 國立交通大學 |
2014-12-08T15:42:07Z |
Design optimization of a current mirror amplifier integrated circuit using a computational statistics technique
|
Li, Yiming; Li, Yih-Lang; Yu, Shao-Ming |
| 國立交通大學 |
2014-12-08T15:42:06Z |
Electronic design automation using a unified optimization framework
|
Li, Yiming; Yu, Shao-Ming; Li, Yih-Lang |
| 國立交通大學 |
2014-12-08T15:37:06Z |
Dead Via Minimization by Simultaneous Routing and Redundant Via Insertion
|
Lin, Chih-Ta; Lin, Yen-Hung; Su, Guan-Chan; Li, Yih-Lang |
| 國立交通大學 |
2014-12-08T15:37:05Z |
Minimizing Clock Latency Range in Robust Clock Tree Synthesis
|
Liu, Wen-Hao; Li, Yih-Lang; Chen, Hui-Chi |
| 國立交通大學 |
2014-12-08T15:36:24Z |
Optimizing the Antenna Area and Separators in Layer Assignment of Multilayer Global Routing
|
Liu, Wen-Hao; Li, Yih-Lang |
| 國立交通大學 |
2014-12-08T15:35:14Z |
Minimizing Critical Area on Grid less Wire Ordering, Sizing and Spacing
|
Lee, Yu-Wei; Lin, Yen-Hung; Li, Yih-Lang |
| 國立交通大學 |
2014-12-08T15:33:11Z |
Routing Congestion Estimation with Real Design Constraints
|
Liu, Wen-Hao; Wei, Yaoguang; Sze, Cliff; Alpert, Charles J.; Li, Zhuo; Li, Yih-Lang; Viswanathan, Natarajan |
| 國立交通大學 |
2014-12-08T15:33:11Z |
Optimization of Placement Solutions for Routability
|
Liu, Wen-Hao; Koh, Cheng-Kok; Li, Yih-Lang |
| 國立交通大學 |
2014-12-08T15:30:13Z |
NCTU-GR 2.0: Multithreaded Collision-Aware Global Routing with Bounded-Length Maze Routing
|
Liu, Wen-Hao; Kao, Wei-Chun; Li, Yih-Lang; Chao, Kai-Yuan |
| 國立交通大學 |
2014-12-08T15:30:08Z |
TRIAD: A Triple Patterning Lithography Aware Detailed Router
|
Lin, Yen-Hung; Yu, Bei; Pan, David Z.; Li, Yih-Lang |
| 國立交通大學 |
2014-12-08T15:30:08Z |
Opening: Introduction to CAD Contest at ICCAD 2012 CAD Contest
|
Jiang, Iris Hui-Ru; Li, Zhuo; Li, Yih-Lang |
| 國立交通大學 |
2014-12-08T15:30:08Z |
A Fast Maze-Free Routing Congestion Estimator With Hybrid Unilateral Monotonic Routing
|
Liu, Wen-Hao; Li, Yih-Lang; Koh, Cheng-Kok |
| 國立交通大學 |
2014-12-08T15:27:29Z |
Critical-Trunk-Based Obstacle-Avoiding Rectilinear Steiner Tree Routings and Buffer Insertion for Delay and Slack Optimization
|
Lin, Yen-Hung; Chang, Shu-Hsin; Li, Yih-Lang |
| 國立交通大學 |
2014-12-08T15:24:33Z |
Topology-Aware Buffer Insertion and GPU-Based Massively Parallel Rerouting for ECO Timing Optimization
|
Lin, Yen-Hung; Lo, Yun-Jian; Tong, Hian-Syun; Liu, Wen-Hao; Li, Yih-Lang |
| 國立交通大學 |
2014-12-08T15:23:05Z |
Optimizing the Antenna Area and Separators in Layer Assignment of Multi-Layer Global Routing
|
Liu, Wen-Hao; Li, Yih-Lang |
| 國立交通大學 |
2014-12-08T15:21:55Z |
NCTU-GR: Efficient Simulated Evolution-Based Rerouting and Congestion-Relaxed Layer Assignment on 3-D Global Routing
|
Dai, Ke-Ren; Liu, Wen-Hao; Li, Yih-Lang |
| 國立交通大學 |
2014-12-08T15:21:18Z |
Gridless Wire Ordering, Sizing and Spacing with Critical Area Minimization
|
Lee, Yu-Wei; Lin, Yen-Hung; Li, Yih-Lang |
| 國立交通大學 |
2014-12-08T15:21:18Z |
Negotiation-Based Layer Assignment for Via Count and Via Overflow Minimization
|
Liu, Wen-Hao; Li, Yih-Lang |
| 國立交通大學 |
2014-12-08T15:21:18Z |
High-Quality Global Routing for Multiple Dynamic Supply Voltage Designs
|
Liu, Wen-Hao; Li, Yih-Lang; Chao, Kai-Yuan |
| 國立交通大學 |
2014-12-08T15:21:11Z |
Topology-Driven Cell Layout Migration with Collinear Constraints
|
Fu, De-Shiun; Chaung, Ying-Zhih; Lin, Yen-Hung; Li, Yih-Lang |
