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机构 日期 题名 作者
國立交通大學 2014-12-08T15:25:55Z Three-dimensional calculation of electronic structures in semiconductor quantum ring based artificial molecules Li, YM
國立交通大學 2014-12-08T15:25:52Z Spin-orbit interaction and energy states in nanoscale semiconductor quantum rings Li, YM
國立交通大學 2014-12-08T15:25:52Z A study of the threshold voltage variations for ultrathin body double gate SOI MOSFETs Tang, CS; Lo, SC; Lee, JW; Tsai, JH; Li, YM
國立交通大學 2014-12-08T15:25:34Z Computer simulation of germanium nanowire field effect transistors Li, YM; Chou, HM; Lee, BS; Lu, CS; Yu, SM
國立交通大學 2014-12-08T15:25:34Z Numerical solutions of master equation for protein folding kinetics Li, YM
國立交通大學 2014-12-08T15:19:39Z A parallel adaptive finite volume method for nanoscale double-gate MOSFETs simulation Li, YM; Yu, SM
國立交通大學 2014-12-08T15:19:23Z Quantum mechanical corrected simulation program with integrated circuit emphasis model for simulation of ultrathin oxide metal-oxide-semiconductor field effect transistor gate tunneling current Li, YM; Yu, SM; Lee, JW
國立交通大學 2014-12-08T15:19:23Z Transition energies of vertically coupled multilayer nanoscale InAs/GaAs semiconductor quantum dots of different shapes Li, YM
國立交通大學 2014-12-08T15:18:51Z A numerical iterative method for solving Schrodinger and Poisson equations in nanoscale single, double and surrounding gate metal-oxide-semiconductor structures Li, YM; Yu, SM
國立交通大學 2014-12-08T15:18:40Z A three-dimensional simulation of electrostatic characteristics for carbon nanotube array field effect transistors Li, YM; Chou, HM; Lee, JW; Lee, BS
國立交通大學 2014-12-08T15:18:30Z Investigation of electrical characteristics on surrounding-gate and omega-shaped-gate nanowire FinFETs Li, YM; Chou, HM; Lee, JW
國立交通大學 2014-12-08T15:18:30Z A comparative study of electrical characteristic on sub-10-nm double-gate MOSFETs Li, YM; Chou, HM
國立交通大學 2014-12-08T15:18:21Z An iterative method for single and vertically stacked semiconductor wuantum dots simulation Li, YM
國立交通大學 2014-12-08T15:16:38Z Effective electrostatic discharge protection circuit design using novel fully silicided N-MOSFETs in sub-100-nm device era. Lee, JW; Li, YM

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