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Taiwan Academic Institutional Repository >
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"liang gee chen"
Showing items 296-305 of 482 (49 Page(s) Totally)
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| 臺大學術典藏 |
2018-09-10T05:15:51Z |
Architecture design of MPEG-2 decoder system
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Lee, Yung-Pin;Chen, Liang-Gee;Ku, Chung-Wei; Lee, Yung-Pin; Chen, Liang-Gee; Ku, Chung-Wei; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T05:15:51Z |
An MPEG audio decoder chip
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Tsai, T.-H.;Chen, L.-G.;Chen, T.-H.; Tsai, T.-H.; Chen, L.-G.; Chen, T.-H.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T05:15:50Z |
VLSI architecture for radix-2k Viterbi decoding with transpose algorithm
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Lee, Wen-Ta;Chen, Thou-Ho;Chen, Liang-Gee; Lee, Wen-Ta; Chen, Thou-Ho; Chen, Liang-Gee; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T05:15:50Z |
An efficient embedded bitstream parsing processor for MPEG-4 video decoding system
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Chang, Y.-C.; Huang, C.-C.; Chao, W.-M.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T05:15:50Z |
Algorithm and architecture optimization for full-mode encoding of H.264/AVC intra prediction
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Tsai, C.-H.; Huang, Y.-W.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T05:15:50Z |
Advances in hardware architectures for image and video coding - A survey
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Tseng, P.-C.; Chang, Y.-C.; Huang, Y.-W.; Fang, H.-C.; Huang, C.-T.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T05:15:50Z |
VLSI-based array dividers with concurrent error detection
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Chen, T.-H.; Lee, Y.-P.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T05:15:49Z |
Architecture of global motion compensation for MPEG-4 advanced simple profile
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Chen, Y.-H.; Chen, C.-Y.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T05:15:49Z |
Architecture design of H.264/AVC decoder with hybrid task pipelining for high definition videos
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Chen, T.-W.; Huang, Y.-W.; Chen, T.-C.; Chen, Y.-H.; Tsai, C.-Y.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T05:15:49Z |
Analysis, fast algorithm, and VLSI architecture design for H.264/AVC intra frame coder
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Huang, Y.-W.; Hsieh, B.-Y.; Chen, T.-C.; Chen, L.-G.; LIANG-GEE CHEN |
Showing items 296-305 of 482 (49 Page(s) Totally)
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