| 臺大學術典藏 |
2018-09-10T04:27:48Z |
Novel systolic array design for the Discrete Hartley Transform with high throughput rate
|
Hsiao, Jue-Husan; Chen, Liang-Gee; Chiueh, Tzi-Dar; Chen, Chun-Te; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T04:27:47Z |
Design of a low power psycho-acoustic model co-processor for MPEG-2/4 AAC LC stereo encoder
|
Tsai, T.-H.; Huang, S.-W.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T04:27:47Z |
Computationally controllable integer, half, and quarter-pel motion estimator for MPEG-4 advanced simple profile
|
Chao, W.-M.; Chen, T.-C.; Chang, Y.-C.; Hsu, C.-W.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T04:27:47Z |
Architecture design for deblocking filter in H.264/JVT/AVC
|
Huang, Y.-W.; Chen, T.-W.; Hsieh, B.-Y.; Wang, T.-C.; Chang, T.-H.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T04:27:46Z |
Hardware oriented rate control algorithm and implementation for realtime video coding
|
Fang, H.-C.; Wang, T.-C.; Chang, Y.-W.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T04:27:46Z |
Hardware implementation of shape-adaptive discrete wavelet transform with the JPEG2000 defaulted (9,7) filter bank
|
Huang, C.-T.; Tseng, P.-C.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T04:27:46Z |
Hardware architecture design for variable block size motion estimation in MPEG-4 AVC/JVT/ITU-T H.264
|
Huang, Y.-W.; Wang, T.-C.; Hsieh, B.-Y.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T04:27:45Z |
Motion adaptive interpolation with horizontal motion detection for deinterlacing
|
Lin, S.-F.; Chang, Y.-L.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T04:27:45Z |
Motion adaptive de-interlacing by horizontal motion detection and enhanced ELA processing
|
Lin, S.-F.; Chang, Y.-L.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T04:27:45Z |
Hardware-oriented optimization and block-level architecture design for MPEG-4 FGS encoder
|
Hsu, C.-W.; Chang, Y.-C.; Chao, W.-M.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T04:27:45Z |
Hardware-efficient architecture design for zerotree coding in MPEG-4 still texture coder
|
Lian, C.-J.; Yang, Z.-L.; Chang, H.-C.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T04:27:44Z |
Performance analysis of hardware oriented algorithm modifications in H.264
|
Fang, H.-C.; Chen, L.-G.; LIANG-GEE CHEN; Huang, Y.-W.; Wang, T.-C. |
| 臺大學術典藏 |
2018-09-10T04:27:44Z |
Novel word-level algorithm of embedded block coding in JPEG 2000
|
Fang, H.-C.; Wang, T.-C.; Chang, Y.-W.; Shih, Y.-Y.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T04:27:44Z |
Motion compensated de-interlacing with adaptive global motion estimation and compensation
|
Chang, Y.-L.; Chen, C.-Y.; Lin, S.-F.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T04:27:44Z |
Parallel 4×4 2D transform and inverse transform architecture for MPEG-4 AVC/H.264
|
Wang, T.-C.; Huang, Y.-W.; Fang, H.-C.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T04:27:43Z |
Reconfigurable discrete wavelet transform architecture for advanced multimedia systems
|
LIANG-GEE CHEN; Chen, L.-G.; Huang, C.-T.; Tseng, P.-C. |
| 臺大學術典藏 |
2018-09-10T04:27:42Z |
VLSI architecture for discrete wavelet transform based on B-spline factorization
|
Huang, C.-T.; Tseng, P.-C.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T04:07:55Z |
ROM-based special purpose multiplication and its applications
|
Jong, H.-M.; Chen, L.-G.; Chiueh, T.-D.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T04:07:55Z |
Language system for DSP silicon compiler
|
Chen, Liang-Gee; Jeng, Lih-Gwo; Tsao, Ki-Tsan; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T04:07:55Z |
DCT-based interframe coding for video codec
|
Jong, H.-M.; Chen, L.-G.; Chiueh, T.-D.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T04:07:55Z |
Automatic synthesizer for CMOS operational amplifiers
|
Kuo, Chin-Yuan; Chen, Liang-Gee; Parng, Tai-Ming; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T04:07:55Z |
Rate-optimal static scheduling for recursive DSP algorithms by retiming and unfolding
|
Jeng, L.-G.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T04:07:55Z |
Design and analysis of VLSI-based arithmetic arrays with error correction
|
Chen, T.-H.; Chen, L.-G.; Jehng, Y.-S.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T04:07:54Z |
An efficient architecture for two-dimensional inverse discrete wavelet transform
|
Wu, P.-C.; Huang, C.-T.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T04:07:54Z |
An efficient and low power architecture design for motion estimation using global elimination algorithm
|
Huang, Y.-W.; Chien, S.-Y.; Hsieh, B.-Y.; Chen, L.-G.; LIANG-GEE CHEN |
