| 臺大學術典藏 |
2018-09-10T05:50:27Z |
Relative depth layer extraction for monoscopic video by use of multidimensional filter
|
Chang, J.-Y.; Cheng, C.-C.; Chien, S.-Y.; Chen, L.-G.; LIANG-GEE CHEN; SHAO-YI CHIEN |
| 臺大學術典藏 |
2018-09-10T05:23:27Z |
Stereo video coding system with hybrid coding based on joint prediction scheme
|
Ding, L.-F.; Chien, S.-Y.; Huang, Y.-W.; Chang, Y.-L.; Chen, L.-G.; LIANG-GEE CHEN; Chien, Shao-Yi |
| 臺大學術典藏 |
2018-09-10T05:23:27Z |
Algorithm and architecture of prediction core in stereo video hybrid coding system
|
Ding, L.-F.; Chien, S.-Y.; Chen, L.-G.; LIANG-GEE CHEN; Chien, Shao-Yi |
| 臺大學術典藏 |
2018-09-10T05:20:41Z |
Reconfigurable platform for content science research
|
Shih, C.-S.; Yang, C.-L.; Ku, M.-K.; Kuo, T.-W.; Chien, S.-Y.; Chang, Y.-W.; Chen, L.-G.; LIANG-GEE CHEN; Shih, Chi-Sheng; Yang, Chia-Lin; TEI-WEI KUO; YAO-WEN CHANG; SHAO-YI CHIEN |
| 臺大學術典藏 |
2018-09-10T05:15:52Z |
A New Block-Matching Criterion for Motion Estimation and its Implementation
|
Lee, Y.-P.; LIANG-GEE CHEN; Chen, M.-J.; Chen, L.-G.; Chiueh, T.-D. |
| 臺大學術典藏 |
2018-09-10T05:15:52Z |
NEW COMPARISON ALGORITHM FOR VERIFYING LOGIC INTERCONNECTION OF VLSI.
|
Chen, L.G.;Lee, J.Y.;Chen, K.T.;Wang, J.F.; Chen, L.G.; Lee, J.Y.; Chen, K.T.; Wang, J.F.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T05:15:51Z |
Very low bit rate video coding system based on optical flow and region segmentation algorithms
|
Ku, Chung-Wei;Chen, Liang-Gee;Chiu, You-Ming; Ku, Chung-Wei; Chen, Liang-Gee; Chiu, You-Ming; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T05:15:51Z |
Pipeline interleaving design for FIR, IIR, and FFT array processors
|
Chen, L.-G.;Jehng, Y.-S.;Chiueh, T.-D.; Chen, L.-G.; Jehng, Y.-S.; Chiueh, T.-D.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T05:15:51Z |
Hardware-oriented design for weighted median filters
|
Chen, Chun-Te;Chen, Liang-Gee;Hsiao, Jue-Hsuan; Chen, Chun-Te; Chen, Liang-Gee; Hsiao, Jue-Hsuan; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T05:15:51Z |
Design and VLSI implementation of MPEG audio decoder
|
Tsai, Tsung-Han;Chen, Thou-Ho;Chen, Liang-Gee; Tsai, Tsung-Han; Chen, Thou-Ho; Chen, Liang-Gee; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T05:15:51Z |
Architecture design of MPEG-2 decoder system
|
Lee, Yung-Pin;Chen, Liang-Gee;Ku, Chung-Wei; Lee, Yung-Pin; Chen, Liang-Gee; Ku, Chung-Wei; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T05:15:51Z |
An MPEG audio decoder chip
|
Tsai, T.-H.;Chen, L.-G.;Chen, T.-H.; Tsai, T.-H.; Chen, L.-G.; Chen, T.-H.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T05:15:50Z |
VLSI architecture for radix-2k Viterbi decoding with transpose algorithm
|
Lee, Wen-Ta;Chen, Thou-Ho;Chen, Liang-Gee; Lee, Wen-Ta; Chen, Thou-Ho; Chen, Liang-Gee; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T05:15:50Z |
An efficient embedded bitstream parsing processor for MPEG-4 video decoding system
|
Chang, Y.-C.; Huang, C.-C.; Chao, W.-M.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T05:15:50Z |
Algorithm and architecture optimization for full-mode encoding of H.264/AVC intra prediction
|
Tsai, C.-H.; Huang, Y.-W.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T05:15:50Z |
Advances in hardware architectures for image and video coding - A survey
|
Tseng, P.-C.; Chang, Y.-C.; Huang, Y.-W.; Fang, H.-C.; Huang, C.-T.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T05:15:50Z |
VLSI-based array dividers with concurrent error detection
|
Chen, T.-H.; Lee, Y.-P.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T05:15:49Z |
Architecture of global motion compensation for MPEG-4 advanced simple profile
|
Chen, Y.-H.; Chen, C.-Y.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T05:15:49Z |
Architecture design of H.264/AVC decoder with hybrid task pipelining for high definition videos
|
Chen, T.-W.; Huang, Y.-W.; Chen, T.-C.; Chen, Y.-H.; Tsai, C.-Y.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T05:15:49Z |
Analysis, fast algorithm, and VLSI architecture design for H.264/AVC intra frame coder
|
Huang, Y.-W.; Hsieh, B.-Y.; Chen, T.-C.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T05:15:49Z |
Analysis and architecture for memory efficient JBIG2 arithmetic encoder
|
Chen, C.-C.; Chang, Y.-W.; Fang, H.-C.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T05:15:48Z |
Hardware architecture design of video compression for multimedia communication systems
|
Chen, Liang-Gee; Chen, Homer H.; Chen, Ching-Yeh; Huang, Yu-Wen; LIANG-GEE CHEN; Chien, Shao-Yi; Chien, Shao-Yi; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T05:15:48Z |
Generic RAM-based architectures for two-dimensional discrete wavelet transform with line-based method
|
Huang, C.-T.; Tseng, P.-C.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T05:15:48Z |
Four field variable block size motion compensated adaptive de-interlacing
|
Chang, Yu-Lin; Chen, Ching-Yeh; Lin, Shyh-Feng; Chen, Liang-Gee; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T05:15:48Z |
Fast filterbanks for the low power MPEG high efficiency advanced audio coding decoder
|
Huang, S.-W.; Tsai, T.-H.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T05:15:48Z |
Fast decomposition of filterbanks for the state-of-the-art audio coding
|
Huang, S.-W.; Tsai, T.-H.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T05:15:47Z |
Memory efficient JPEG 2000 architecture with stripe pipeline scheme
|
Fang, H.-C.; Chang, Y.-W.; Cheng, C.-C.; Chen, C.-C.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T05:15:47Z |
Memory analysis of VLSI architecture for 5/3 and 1/3 motion-compensated temporal filtering
|
Huang, C.-T.; Chen, C.-Y.; Chen, Y.-H.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T05:15:47Z |
JPEG, MPEG-4, and H.264 codec IP development
|
Lian, Chung-Jr; Huang, Yu-Wen; Fang, Hung-Chi; Chang, Yung-Chi; Chen, Liang-Gee; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T05:15:47Z |
Hybrid-mode embedded compression for H.264/AVC video coding system
|
Chen, T.-C.; Chen, Y.-H.; Wu, K.-C.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T05:15:47Z |
Hardware oriented content-adaptive fast algorithm for variable block-size integer motion estimation in H.264
|
Chen, Y.-H.; Chen, T.-C.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T05:15:46Z |
Parallel embedded block coding architecture for JPEG 2000
|
Fang, H.-C.; Chang, Y.-W.; Wang, T.-C.; Lian, C.-J.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T05:15:46Z |
One-pass computation-aware motion estimation with adaptive search strategy
|
Huang, Y.W.; Lee, C.L.; Chen, C.Y.; Chen, L.G.; LIANG-GEE CHEN; Lee, Chia-Lin |
| 臺大學術典藏 |
2018-09-10T05:15:46Z |
Nearly lossless content-dependent low-power DCT design for mobile video applications
|
Lin, C.-P.; Tseng, P.-C.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T05:15:46Z |
Multiple-lifting Scheme: Memory-efficient VLSI implementation for line-based 2-D DWT
|
Cheng, C.-C.; Huang, C.-T.; Tseng, P.-C.; Pan, C.-H.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T05:15:46Z |
Multi-mode embedded compression codec engine for power-aware video coding system
|
Cheng, C.-C.; Tseng, P.-C.; Huang, C.-T.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T05:15:45Z |
Special issue on advances in video coding and delivery
|
Zhu, W.; Sun, M.-T.; Chen, L.-G.; Sikora, T.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T05:15:45Z |
Reconfigurable discrete wavelet transform processor for heterogeneous reconfigurable multimedia systems
|
Tseng, P.-C.;Huang, C.-T.;Chen, L.-G.; Tseng, P.-C.; Huang, C.-T.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T05:15:44Z |
VLSI architecture for forward discrete wavelet transform based on B-spline factorization
|
Huang, C.-T.; Tseng, P.-C.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T05:15:44Z |
VLSI architecture for fifting-based shape-adaptive discrete wavelet transform with odd-symmetric filters
|
Huang, C.-T.; Tseng, P.-C.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T05:15:44Z |
Video de-interlacing by adaptive 4-field global/local motion compensated approach
|
Chang, Y.-L.; Lin, S.-F.; Chen, C.-Y.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T04:47:25Z |
High throughput CORDIC-based systolic array design for the discrete cosine transform
|
Hsiao, Jue-Hsuan; Chen, Liang-Gee; Chiueh, Tzi-Dar; Chen, Chun-Te; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T04:47:25Z |
Design and VLSI implementation of real-time weighted median filters
|
Hsiao, Jue-Hsuan; LIANG-GEE CHEN; Chen, Chun-Te;Chen, Liang-Gee;Chiueh, Tzi-Dar;Hsiao, Jue-Hsuan; Chen, Chun-Te; Chen, Liang-Gee; Chiueh, Tzi-Dar |
| 臺大學術典藏 |
2018-09-10T04:47:25Z |
Chip design of A 32-b logarithmic number system
|
Huang, Sheng-Chieh;Chen, Liang-Gee;Chen, Thou-Ho; Huang, Sheng-Chieh; Chen, Liang-Gee; Chen, Thou-Ho; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T04:47:25Z |
Application-specific chip design using behavioral silicon compiler
|
Chen, Liang-Gee; Jeng, Lih-Gwo; Lin, Dong-Jye; LIANG-GEE CHEN; Chen, Liang-Gee;Jeng, Lih-Gwo;Lin, Dong-Jye |
| 臺大學術典藏 |
2018-09-10T04:47:25Z |
Accuracy Improvement and Cost Reduction of 3-Step Search Block Matching Algorithm for Video Coding
|
Jong, H.-M.;Chen, L.-G.;Chiueh, T.-D.; Jong, H.-M.; Chen, L.-G.; Chiueh, T.-D.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T04:47:25Z |
A High Quality MC-OBTC Codec for Video Signal Processing
|
Chen, L.-G.;Liu, Y.-C.; Chen, L.-G.; Liu, Y.-C.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T04:47:24Z |
Parallel architectures of 3-step search block-matching algorithm for video coding
|
Jong, Her-Ming;Chen, Liang-Gee;Chiueh, Tzi-Dar; Jong, Her-Ming; Chen, Liang-Gee; Chiueh, Tzi-Dar; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T04:47:24Z |
Parallel Architectures for 3-Step Hierarchical Search Block-Matching Algorithm
|
Jong, H.-M.;Chen, L.-G.;Chiueh, T.-D.; Jong, H.-M.; Chen, L.-G.; Chiueh, T.-D.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T04:47:24Z |
One-dimensional full search motion estimation algorithm for video coding
|
Chen, Mei-Juan; Chen, Liang-Gee; Chiueh, Tzi-Dar; LIANG-GEE CHEN |
