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"liang gee chen"的相關文件
顯示項目 341-365 / 482 (共20頁)
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| 臺大學術典藏 |
2018-09-10T04:47:23Z |
Tree-structure architecture and VLSI implementation for vector quantization algorithms
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Ku, Chung-Wei;Chen, Liang-Gee;Chiueh, Tzi-Dar;Jong, Her-Ming; Ku, Chung-Wei; Chen, Liang-Gee; Chiueh, Tzi-Dar; Jong, Her-Ming; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T04:47:23Z |
Rate-Optimal DSP Synthesis by Pipeline and Minimum Unfolding
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Jeng, L.-G.;Chen, L.-G.; Jeng, L.-G.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T04:47:23Z |
Radix-2k Viterbi decoding with transpose path metric processor
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Lee, Wen-Ta;Chen, Thou-Ho;Chen, Liang-Gee; Lee, Wen-Ta; Chen, Thou-Ho; Chen, Liang-Gee; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T04:47:22Z |
Extended intelligent EDGE-based line average with its implementation and test method
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Chang, Y.-L.;Lin, S.-F.;Chen, L.-G.; Chang, Y.-L.; Lin, S.-F.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T04:47:22Z |
B-spline factorization-based architecture for inverse discrete wavelet transform
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Huang, C.-T.;Tseng, P.-C.;Chen, L.-G.; Huang, C.-T.; Tseng, P.-C.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T04:47:22Z |
Architecture of MPEG-7 color structure description generator for realtime video applications
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Chang, J.-Y.; Fang, H.-C.; Huang, Y.-W.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T04:47:22Z |
Architecture and analysis of color structure descriptor for real-time video indexing and retrieval
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Chang, J.-Y.;Lian, C.-J.;Fang, H.-C.;Chen, L.-G.; Chang, J.-Y.; Lian, C.-J.; Fang, H.-C.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T04:47:22Z |
Architecture and analysis of color structure and scalable color descriptor for real-time video indexing and retrieval
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Chang, J.-Y.;Lian, C.-J.;Chen, L.-G.; Chang, J.-Y.; Lian, C.-J.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T04:47:22Z |
Analysis and design of macroblock pipelining for H.264/AVC VLSI architecture
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Chen, T.-C.;Huang, Y.-W.;Chen, L.-G.; Chen, T.-C.; Huang, Y.-W.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T04:47:21Z |
Hardware architecture design for H.264/AVC intra frame coder
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Huang, Y.-W.; Hsieh, B.-Y.; Chen, T.-C.; Chen, L.-G.; Huang, Y.-W.; Hsieh, B.-Y.; Chen, T.-C.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T04:47:21Z |
Fully utilized and reusable architecture for fractional motion estimation of H.264/AVC
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Chen, T.-C.;Huang, Y.-W.;Chen, L.-G.; Chen, T.-C.; Huang, Y.-W.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T04:47:21Z |
Four field local motion compensated de-interlacing
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Chang, Y.-L.;Wu, P.-H.;Lin, S.-F.;Chen, L.-G.; Chang, Y.-L.; Wu, P.-H.; Lin, S.-F.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T04:47:21Z |
Flipping Structure: An Efficient VLSI Architecture for Lifting-Based Discrete Wavelet Transform
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Huang, C.-T.; Tseng, P.-C.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T04:47:20Z |
Hardware architecture design for visual processing: Present and future
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Tseng, P.-C.; Chen, L.-G.; Tseng, P.-C.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T04:47:19Z |
Hardware architecture for global motion estimation for MPEG-4 advanced simple profile
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Chen, C.-Y.; Chien, S.-Y.; Chao, W.-M.; Huang, Y.-W.; Chen, L.-G.; Chen, C.-Y.; Chien, S.-Y.; Chao, W.-M.; Huang, Y.-W.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T04:47:19Z |
High performance two-symbol arithmetic encoder in JPEG 2000
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Chang, Y.-W.; Fang, H.-C.; Chen, L.-G.; Chang, Y.-W.; Fang, H.-C.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T04:47:18Z |
Multi-mode content-aware motion estimation algorithm for power-aware video coding systems
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Lin, S.-S.;Tseng, P.-C.;Lin, C.-P.;Chen, L.-G.; Lin, S.-S.; Tseng, P.-C.; Lin, C.-P.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T04:47:18Z |
MPEG-4 FGS Encoder design for an interactive content-aware MPEG-4 video streaming SOC
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Chang; Y.-C.; Hsu; C.-W.; Chen; L.-G.; Chang; Y.-C.; Hsu; C.-W.; Chen; L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T04:47:18Z |
Memory analysis and architecture for two-dimensional discrete wavelet transform
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Huang, C.-T.; Tseng, P.-C.; Chen, L.-G.; Huang, C.-T.; Tseng, P.-C.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T04:47:18Z |
LSI design for MPEG-4 coding system
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Chang, Y.-C.;Chao, W.-M.;Chen, L.-G.; Chang, Y.-C.; Chao, W.-M.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T04:47:18Z |
Low-power parallel tree architecture for full search block-matching motion estimation
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Lin, S.-S.; Tseng, P.-C.; Chen, L.-G.; Lin, S.-S.; Tseng, P.-C.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T04:47:17Z |
Reconfigurable discrete cosine transform processor for object-based video signal processing
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Tseng, P.-C.; Haung, C.-T.; Chen, L.-G.; LIANG-GEE CHEN; Tseng, P.-C.; Haung, C.-T.; Chen, L.-G. |
| 臺大學術典藏 |
2018-09-10T04:47:17Z |
Power-efficient FIR filter architecture design for wireless embedded system
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Lin, S.-F.;Huang, S.-C.;Yang, F.-S.;Ku, C.-W.;Chen, L.-G.; Lin, S.-F.; Huang, S.-C.; Yang, F.-S.; Ku, C.-W.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T04:47:17Z |
Platform-based MPEG-4 video encoder soc design
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Chang, Y.-C.;Chao, W.-M.;Chen, L.-G.; Chang, Y.-C.; Chao, W.-M.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T04:47:17Z |
Parallel global elimination algorithm and architecture design for fast block matching motion estimation
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Huang, Y.-W.; Tsai, C.-H.; Chen, L.-G.; Huang, Y.-W.; Tsai, C.-H.; Chen, L.-G.; LIANG-GEE CHEN |
顯示項目 341-365 / 482 (共20頁)
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