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教育部委託研究計畫 計畫執行:國立臺灣大學圖書館
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"liang gee chen"的相關文件
顯示項目 401-410 / 482 (共49頁)
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每頁顯示[10|25|50]項目
| 臺大學術典藏 |
2018-09-10T04:07:55Z |
Automatic synthesizer for CMOS operational amplifiers
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Kuo, Chin-Yuan; Chen, Liang-Gee; Parng, Tai-Ming; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T04:07:55Z |
Rate-optimal static scheduling for recursive DSP algorithms by retiming and unfolding
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Jeng, L.-G.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T04:07:55Z |
Design and analysis of VLSI-based arithmetic arrays with error correction
|
Chen, T.-H.; Chen, L.-G.; Jehng, Y.-S.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T04:07:54Z |
An efficient architecture for two-dimensional inverse discrete wavelet transform
|
Wu, P.-C.; Huang, C.-T.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T04:07:54Z |
An efficient and low power architecture design for motion estimation using global elimination algorithm
|
Huang, Y.-W.; Chien, S.-Y.; Hsieh, B.-Y.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T04:07:54Z |
A novel hybrid motion estimator supporting diamond search and fast full search
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Chao, W.-M.; Hsu, C.-W.; Chang, Y.-C.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T04:07:54Z |
A hardware accelerator for video segmentation using programmable morphology PE array
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Chien, S.-Y.; Huang, Y.-W.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T04:07:54Z |
A digital signal processor with programmable correlator array architecture for third generation wireless communication system
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Chen, C.-K.; Tseng, P.-C.; Chang, Y.-C.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T04:07:53Z |
Computation reduction technique for lossy JPEG2000 encoding through EBCOT tier-2 feedback processing
|
Chang, T.-H.; Chen, L.-L.; Lian Jr.; C.; Chen, H.-H.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T04:07:53Z |
Automatic threshold decision of background registration technique for video segmentation
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Huang, Y.-W.; Chien, S.-Y.; Hsieh, B.-Y.; Chen, L.-G.; LIANG-GEE CHEN; SHAO-YI CHIEN |
顯示項目 401-410 / 482 (共49頁)
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每頁顯示[10|25|50]項目
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