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Showing items 81-87 of 87 (4 Page(s) Totally)
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| 國立臺灣大學 |
1992-10 |
A BiCMOS dynamic full adder circuit for VLSI implementation of high-speed parallel multipliers using Wallace tree reduction architecture
|
Kuo, J.B.; Liao, H.J.; Chen, H.P. |
| 臺大學術典藏 |
1992-10 |
A BiCMOS dynamic full adder circuit for VLSI implementation of high-speed parallel multipliers using Wallace tree reduction architecture
|
Kuo, J.B.; Liao, H.J.; Chen, H.P.; Kuo, J.B.; Liao, H.J.; Chen, H.P.; KuoJB |
| 國立臺灣大學 |
1992-06 |
BiCMOS dynamic full adder circuit for high-speed parallel multipliers
|
Chen, H.P.; Liao, H.J.; Kuo, J.B. |
| 國立臺灣大學 |
1992-02 |
BiCMOS dynamic Manchester carry look ahead circuit for high speed arithmetic unit VLSI
|
Kuo, J.B.; Liao, H.J.; Chen, H.P. |
| 臺大學術典藏 |
1992-02 |
BiCMOS dynamic Manchester carry look ahead circuit for high speed arithmetic unit VLSI
|
Kuo, J.B.; Liao, H.J.; Chen, H.P.; KuoJB; Kuo, J.B.; Liao, H.J.; Chen, H.P. |
| 國立臺灣大學 |
1991-09 |
A BiCMOS tristate buffer for high-speed microprocessor VLSI
|
Kuo, J.B.; Liao, H.J. |
| 臺大學術典藏 |
1991-09 |
A BiCMOS tristate buffer for high-speed microprocessor VLSI
|
Kuo, J.B.; Liao, H.J.; Kuo, J.B.; Liao, H.J.; KuoJB |
Showing items 81-87 of 87 (4 Page(s) Totally)
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